Cosmic-ray immune latch circuit for 90nm technology and beyond

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages 492-493

  Arima, Yukio ^a,b   Yamashita, Takahiro ^a   Komatsu, Yoshihide ^a   Fujimoto, Tetsuya ^a   Ishibashi, Koichiro ^a  

^a STARC   (Japan)

^b PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT CONFIGURATION; FAILURE NODE; IMMUNE LATCH; NOISE CHARGE;

COSMIC RAYS; ELECTRONS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; NEUTRON RADIOGRAPHY; SILICON;

LSI CIRCUITS;

EID: 2442690733     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. D. Bradley, P. Mahoney, B. Stackhouse, "The 16kB Single-Cycle Read Access Cache on a Next-Generation 64b Itanium Microprocessor," ISSCC Dig. Tech. Papers, pp. 110-111, Feb. 2002
2. K. Osada, Y. Saitoh, E. Ibe, K. Ishibashi, "16.7fA/cell Tunnel-Leakage-Suppressed 16Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors," ISSCC Dig. Tech. Papers, Feb. 2003.
3. Y. Tosaka, "Simple Method for Estimating Neutron-Induced Soft Error Rates Based on Modified BGR Model," IEEE Electron Device Letters, vol. 20, no. 2, pp. 89-91, Feb. 1999
4. T. Karnik et al, "Selective Node Engineering for Chip-Level Soft Error Rate Improvement," Symposium VLSI Circuits Dig., pp. 204-205, Jun. 2002.
5. K. J. Hass, J. W. Gambles, "Mitigating Single Event Upsets from Combinational Logic," 7th NASA Symposium on VLSI Design, 1998