Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 665-670

  Goel, Ashish ^a   Bhunia, Swarup ^b   Mahmoodi, Hamid ^c   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b CASE WESTERN RESERVE UNIVERSITY   (United States)

^c SAN FRANCISCO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; EQUIPMENT TESTING; ERROR CORRECTION; ERROR DETECTION; HARDWARE; INTEGRATED CIRCUIT LAYOUT;

CIRCUIT DESIGN; COMBINATIONAL PATH TESTABILITY; DELAY FAULT TESTING; SOFT ERROR DETECTION;

FLIP FLOP CIRCUITS;

EID: 33748587814     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118456     Document Type: Conference Paper

References (12)

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