Design space exploration for multicore architectures: A power/performance/thermal view

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2006, Pages 177-186

  Monchiero, Matteo ^a   Canal, Ramon ^b   González, Antonio ^c  

^a POLITECNICO DI MILANO   (Italy)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT LAYOUT; PARALLEL PROCESSING SYSTEMS; STORAGE ALLOCATION (COMPUTER);

DESIGN SPACE EXPLORATION; MEMORY HIERARCHY; MULTICORE ARCHITECTURES;

MICROPROCESSOR CHIPS;

EID: 34547425357     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1183401.1183428     Document Type: Conference Paper

References (29)

1. C. McNairy and R. Bhatia. Montecito: A dual-core, dual-thread Itanium processor. IEEE Micro, pages 10-20, March/April 2005.
2. P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded Sparc processor. IEEE Micro, pages 21-29, March/April 2005.
3. R. Kalla, B. Sinharoy, and J.M. Tendler. IBM Power5 Chip: A Dual-Core Multithreaded Processor. IEEE MICRO, pages 40-47, March/April 2004.
4. Trevor Mudge. Power: A first class constraint for future architectures. In HPCA '00: Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Washington, DC, USA, 2000. IEEE Computer Society.
5. Kevin Skadron, Mircea R. Stan, Karthik Sankaranarayanan, Wei Huang, Sivakumar Velusamy, and David Tarjan. Temperature-aware microarchitecture: Modeling and implementation. ACM Trans. Archit. Code Optim., 1(1):94-125, 2004.
6. Intel. White paper: Superior performance with dual-core. Technical report, Intel, 2005.
7. Kelly Quinn, Jessica Yang, and Vernon Turner. The next evolution in enterprise computing: The convergence of multicore x86 processing and 64-bit operating systems - white paper. Technical report, Advanced Micro Devices Inc., April 2005.
8. Jose Renau, Basilio Fraguela, James Tuck, Wei Liu, Milos Prvulovic, Luis Ceze, Smruti Sarangi, Paul Sack, Karin Strauss, and Pablo Montesinos. SESC simulator, January 2005. http://sesc.sourceforge.net.
9. David Brooks, Vivek Tiwari, and Margaret Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In Proc. of the 27th International Symposium on Computer Architecture, pages 83-94. ACM Press, 2000.
10. Premkishore Shivakumar and Norman P. Jouppi. CACTI 3.0: An integrated cache timing, power, and area model. Technical Report 2001/2, Western Research Laboratory, Compaq, 2001.
11. J. Huh, D. Burger, and S. Keckler. Exploring the design space of future cmps. In PACT'01: Proceedings of the 10th International Conference on Parallel Architectures and Compilation Techniques, pages 199-210, Washington, DC, USA, 2001. IEEE Computer Society.
12. M. Ekman and P. Stenstrom. Performance and power impact of issue-width in chip-multiprocessor cores. In ICPP'03: Proceedings of the 2003 International Conference on Parallel Processing, pages 359-369, Washington, DC, USA, 2003. IEEE Computer Society.
13. Stefanos Kaxiras, Girija Narlikar, Alan D. Berenbaum, and Zhigang Hu. Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads. In CASES '01: Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, pages 211-220, New York, NY, USA, 2001. ACM Press.
14. Ed Grochowski, Ronny Ronen, John Shen, and Hong Wang. Best of both latency and throughput. In ICCD '04: Proceedings of the IEEE International Conference on Computer Design (ICCD'04), pages 236-243, Washington, DC, USA, 2004. IEEE Computer Society.
15. J. Li and J.F. Martinez. Power-performance implications of thread-level parallelism on chip multiprocessors. In ISPASS'05: Proceedings of the 2005 International Symposium on Performance Analysis of Systems and Software, pages 124-134, Washington, DC, USA, 2005. IEEE Computer Society.
16. J. Li and J.F. Martinez. Dynamic power-performance adaptation of parallel computation on chip multiprocessors. In HPCA '06: Proceedings of the 12th International Symposium on High Performance Computer Architecture, Washington, DC, USA, 2006. IEEE Computer Society.
17. Yingmin Li, David Brooks, Zhigang Hu, and Kevin Skadron. Performance, energy, and thermal considerations for SMT and CMP architectures. In HPCA '05: Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pages 71-82, Washington, DC, USA, 2005. IEEE Computer Society.
18. Y. Li, B. Lee, D. Brooks, Z. Hu, and K. Skadron. CMP design space exploration subject to physical constraints. In HPCA '06: Proceedings of the 12th International Symposium on High Performance Computer Architecture, Washington, DC, USA, 2006. IEEE Computer Society.
19. Rakesh Kumar, Victor Zyuban, and Dean M. Tullsen. Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling. In ISCA '05: Proceedings of the 32nd Annual International Symposium on Computer Architecture, pages 408-419, Washington, DC, USA, 2005. IEEE Computer Society.
20. K. Sankaranarayanan, S. Velusamy, M. Stan, and K. Skadron. A case for thermal-aware floorplanning at the microarchitectural level. Journal of Instruction Level Parallelism, 2005.
21. Pedro Chaparro, Grigorios Magklis, Jose Gonzalez, and Antonio Gonzalez. Distributing the frontend for temperature reduction. In HPCA '05: Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pages 61-70, Washington, DC, USA, 2005. IEEE Computer Society.
22. Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, and Yehea Ismail. Thermal management of on-chip caches through power density minimization. In MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, pages 283-293, Washington, DC, USA, 2005. IEEE Computer Society.
23. V. Zyuban and P. N. Strenski. Balancing hardware intensity in microprocessor pipelines. IBM Journal of Research & Development, 47(5-6):585-598, 2003.
24. R. E. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24.
25. Subbarao Palacharla, Norman P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. In ISCA '97: Proceedings of the 24th annual international symposium on Computer architecture, pages 206-218, New York, NY, USA, 1997. ACM Press.
26. Hang-Sheng Wang, Xinping Zhu, Li-Shiuan Peh, and Sharad Malik. Orion: a power-performance simulator for interconnection networks. In Proc. of the 35th annual ACM/IEEE International Symposium on Microarchitecture, pages 294-305, 2002.
27. Weiping Liao, Lei He, and K.M. Lepak. Temperature and supply Voltage aware performance and power modeling at microarchitecture level. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(7): 1042.
28. Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, and Anoop Gupta. The SPLASH-2 programs: characterization and methodological considerations. In ISCA '95: Proceedings of the 22nd annual International Symposium on Computer Architecture, pages 24-36, New York, NY, USA, 1995. ACM Press.
29. Man-Lap Li, Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, and Eric Debes. The alpbench benchmark suite for complex multimedia applications. In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC-2005), Washington, DC, USA, 2005. IEEE Computer Society.