Distributing the frontend for temperature reduction

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2005, Pages 61-70

  Chaparro, Pedro ^a   Magklis, Grigorios ^a   González, José ^a   González, Antonio ^a  

^a Intel Research Cambridge Lab   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

MICROARCHITECTURE; PEAK TEMPERATURES; TEMPERATURE REDUCTION; THERMAL EMERGENCIES;

BUFFER STORAGE; FUNCTIONS; HEAT LOSSES; MAPPING; THERMAL EFFECTS; THROUGHPUT;

MICROPROCESSOR CHIPS;

EID: 28444447997     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2005.12     Document Type: Conference Paper

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