Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 10, 2005, Pages 1127-1135

  Wang, Hua ^a   Miranda, M ^a   Papanikolaou, A ^a   Catthoor, F ^a   Dehaene, W ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

65 nm; Aphilipp; CMOS nanometer technology; Embedded SRAM; Formalized technique; Pareto configurations; Pareto optimal energy delay tradeoffs; Run time configuration; Transistor level implementation; Variable tapered Pareto buffer design

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; EMBEDDED SYSTEMS; NANOTECHNOLOGY; PARETO PRINCIPLE; TRANSISTORS;

EMBEDDED SRAM; FORMALIZED TECHNIQUE; RUN-TIME CONFIGURATION; VARIABLE TAPERED PARETO BUFFER DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 31144433907     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.859480     Document Type: Article

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