BMSYN: Bus matrix communication architecture synthesis for MPSoC

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 8, 2007, Pages 1454-1464

  Pasricha, Sudeep ^a,b   Dutt, Nikil D ^a,b   Ben Romdhane, Mohamed ^a,c  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Newport Media Inc   (United States)

Author keywords

Communication system performance; Digital systems; High level synthesis

Indexed keywords

BANDWIDTH CONSTRAINTS; COMMUNICATION SYSTEM PERFORMANCE; DIGITAL SYSTEMS; HIGH LEVEL SYNTHESIS;

BANDWIDTH COMPRESSION; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; MICROPROCESSOR CHIPS; OPTIMIZATION; TELECOMMUNICATION SYSTEMS;

MULTIPROCESSING SYSTEMS;

EID: 34547226012     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.891376     Document Type: Article

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