Tradeoffs between gate oxide leakage and delay for dual T ox circuits

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 761-766

  Sultania, Anup Kumar ^a   Sylvester, Dennis ^b   Sapatnekar, Sachin S ^a  

^a University of Minnesota   (United States)

^b University of Michigan   (United States)

Author keywords

Dual T ox Circuits; Leakage power

Indexed keywords

DUAL TOX CIRCUITS; LEAKAGE POWER; STATIC TIMING ANALYSIS (STA);

ALGORITHMS; CAPACITANCE; COMPUTER SIMULATION; ITERATIVE METHODS; LEAKAGE CURRENTS; MATHEMATICAL MODELS; TRANSCONDUCTANCE; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 4444319095     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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