Power-constrained test scheduling for multi-clock domain SoCs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Yoneda, Tomokazu ^a   Masuda, Kimihiko ^b   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS CONTROL; ALGORITHMS; ELECTRIC POWER UTILIZATION; OPTIMIZATION; VIRTUAL REALITY;

CLOCK FREQUENCIES; TEST SCHEDULING ALGORITHM;

MICROPROCESSOR CHIPS;

EID: 34047184886     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244142     Document Type: Conference Paper

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