Test cost reduction for SOCs using virtual TAMs and lagrange multipliers

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 738-743

  Sehgal, Anuja ^a   Iyengar, Vikram ^b   Krasniewski, Mark D ^a   Chakrabarty, Krishnendu ^a  

^a Duke University   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

Automatic test equipment (ATE); Bandwidth matching; Scan chains; System on chip (SOC); Test access mechanism (TAM)

Indexed keywords

ALGORITHMS; FREQUENCIES; INTEGRATED CIRCUIT TESTING; LAGRANGE MULTIPLIERS; OPTIMIZATION;

TEST ACCESS MECHANISM (TAM);

MICROPROCESSOR CHIPS;

EID: 0042635598     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/776019.776021     Document Type: Conference Paper

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