Multi-frequency wrapper design and optimization for embedded cores under average power constraints

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 123-128

  Xu, Qiang ^a   Nicolici, Nicola ^a   Chakrabarty, Krjshnendu ^b  

^a MCMASTER UNIVERSITY   (Canada)

^b DUKE UNIVERSITY   (United States)

Author keywords

Multiple Clock Domains; Scan Control Unit; Wrapper Design

Indexed keywords

CONSTRAINT THEORY; FREQUENCIES; HEURISTIC METHODS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; OPTIMIZATION;

INTEGER LINEAR PROGRAMMING (ILP); MULTIPLE CLOCK DOMAINS; SCAN CONTROL UNIT; WRAPPER DESIGN;

EMBEDDED SYSTEMS;

EID: 27944438868     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193785     Document Type: Conference Paper

References (21)

1. S. K. Goel and E. J. Marinissen. Control-Aware Test Architecture Design for Modular SOC Testing. In Proceedings IEEE European Test Workshop (ETW), pages 57-62, Maastricht, The Netherlands, May 2003.
2. V. lyengar, K. Chakrabarty, and E. J. Marinissen. Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores. Journal of Electronic Testing: Theory and Applications, 18(2):213-230, Apr. 2002.
3. V. Jain and J. Waicukauski. Scan Test Data Volume Reduction in Multi-clocked Designs with Safe Capture Technique. In Proceedings IEEE International Test Conference (ITC), pages 148 -153, Oct. 2002.
4. A. Khoche. Test Resource Partitioning for Scan Architectures Using Bandwidth Matching. In Digest of Int. Workshop on Test Resource Partitioning, pages 1.4.1-1.4.8, 2002.
5. S. Koranne. A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm. Journal of Electronic Testing: Theory and Applications, 18(4/5):415-434, Aug. 2002.
6. E. Larsson and Z. Peng. A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling. In Proceedings IEEE International Test Conference (ITC), pages 1135-1144, Charlotte, NC, Sept. 2003.
7. X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, and N. Tamarapalli. High-Frequency, At-Speed Scan Testing. IEEE Design & Test of Computers, 20(5): 17-25, Oct 2003.
8. X. Lin and R. Thompson. Test generation for designs with multiple clocks. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 662-667, 2003.
9. E. J. Marinissen et al. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores. In Proceedings IEEE International Test Conference (ITC), pages 284-293, Washington, DC, Oct. 1998.
10. E. J. Marinissen et al. On IEEE P1500's Standard for Embedded Core Test. Journal of Electronic Testing: Theory and Applications, 18(4/5):365-383, Aug. 2002.
11. E. J. Marinissen, S. K. Goel, and M. Lousberg. Wrapper Design for Embedded Core Test. In Proceedings IEEE International Test Conference (ITC), pages 911-920, Atlantic City, NJ, Oct. 2000.
12. N. Nicolici and B. M. Al-Hashimi. Power-Constrained Testing of VLSI Circuits. Kluwer Academic Publishers, 2003.
13. S. Pateras. Achieving At-Speed Stuctural Test. IEEE Design & Test of Computers, 20(5):26-33, Oct 2003.
14. J. Schmid and J. Knablein. Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs. In Proceedings IEEE VLSI Test Symposium (VTS), pages 106 -113, 1999.
15. H. Schwab. Lp solve. In http://elib.zib.de/pub/Packages/mathprog/linprog/ lp-solve, 1997.
16. A. Sehgal and K. Chakrabarty. Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. In Proceedings Design, Automation, and Test in Europe (DATE), pages 422-427, Paris, France, Feb. 2004.
17. Technical White Paper. Designs with Multiple Clock Domains: Avoiding Clock Skew and Reducing Pattern Count Using DFT Advisor and Fast Scan. http://www.mentor.com/dft.
18. N. Tendolkar, R. Raina, R. Woltenberg, X. Lin, B. Swanson, and G. Aldrich. Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola Microprocessors Based on PowerPC Instruction Set Architecture. In Proceedings IEEE VLSI Test Symposium (VTS), pages 3-8, 2002.
19. B. Vermeulen, S. Oostdijk, and F. Bouwman. Test and Debug Strategy of the PNX8525 Nexperia™ Digital Video Platform System Chip. In Proceedings IEEE International Test Conference (ITC), pages 121-130, Oct. 2001.
20. D. Wu, M. Lin, S. Mitra, K. S. Kim, A. Sabbavarapu, T. Jaber, P. Johnson, D. March, and G. Parrish. H-DFT: A Hybrid DFT Architecture for Low-Cost High Quality Structural Testing. In Proceedings IEEE International Test Conference (ITC), pages 1229 - 1238, 2003.
21. Q. Xu and N. Nicolici. Wrapper Design for Testing IP Cores with Multiple Clock Domains. In Proceedings Design, Automation, and Test in Europe (DATE), pages 416-421, Paris, France, Feb. 2004.