-
1
-
-
50949100112
-
A flexible power model for FPGAs
-
Sep
-
K. Poon, A. Yan, and S. Wilton, "A flexible power model for FPGAs," in Proc. 12th Int. Conf. Field-Programmable Logic and Appl., Sep. 2002, pp. 312-321.
-
(2002)
Proc. 12th Int. Conf. Field-Programmable Logic and Appl
, pp. 312-321
-
-
Poon, K.1
Yan, A.2
Wilton, S.3
-
2
-
-
0038687619
-
Architecture evaluation for power-efficient FPGAs
-
Feb
-
F. Li, D. Chen, L. He, and J. Cong, "Architecture evaluation for power-efficient FPGAs," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2003, pp. 175-184.
-
(2003)
Proc. ACM Int. Symp. Field-Programmable Gate Arrays
, pp. 175-184
-
-
Li, F.1
Chen, D.2
He, L.3
Cong, J.4
-
4
-
-
2442466857
-
Active leakage power optimization for FPGAs
-
Feb
-
J. H. Anderson, F. N. Najm, and T. Tuan, "Active leakage power optimization for FPGAs," in Proc. ACM Int. Symp, Field-Programmable Gate Arrays, Feb. 2004, pp. 33-41.
-
(2004)
Proc. ACM Int. Symp, Field-Programmable Gate Arrays
, pp. 33-41
-
-
Anderson, J.H.1
Najm, F.N.2
Tuan, T.3
-
5
-
-
0346148417
-
On the interaction between power-aware FPGA CAD algorithms
-
Nov
-
J. Lamoureux and S. J. Wilton, "On the interaction between power-aware FPGA CAD algorithms," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2003, pp. 701-708.
-
(2003)
Proc. Int. Conf. Comput.-Aided Des
, pp. 701-708
-
-
Lamoureux, J.1
Wilton, S.J.2
-
6
-
-
2442474225
-
Reducing leakage energy in FPGAs using region-constrained placement
-
Feb
-
A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and T. Tuan, "Reducing leakage energy in FPGAs using region-constrained placement," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2004, pp. 51-58.
-
(2004)
Proc. ACM Int. Symp. Field-Programmable Gate Arrays
, pp. 51-58
-
-
Gayasen, A.1
Tsai, Y.2
Vijaykrishnan, N.3
Kandemir, M.4
Irwin, M.J.5
Tuan, T.6
-
7
-
-
0036911921
-
Managing power and performance for system-on-chip designs using voltage islands
-
D. E. Lackey et al., "Managing power and performance for system-on-chip designs using voltage islands," in Proc. Int. Conf. Comput.-Aided Des., 2002, pp. 195-202.
-
(2002)
Proc. Int. Conf. Comput.-Aided Des
, pp. 195-202
-
-
Lackey, D.E.1
-
8
-
-
2442422090
-
Low-power FPGA using predefined dual-Vdd/dual-Vt fabrics
-
Feb
-
F. Li, Y. Lin, L. He, and J. Cong, "Low-power FPGA using predefined dual-Vdd/dual-Vt fabrics," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2004, pp. 42-50.
-
(2004)
Proc. ACM Int. Symp. Field-Programmable Gate Arrays
, pp. 42-50
-
-
Li, F.1
Lin, Y.2
He, L.3
Cong, J.4
-
9
-
-
4444343168
-
FPGA power reduction using configurable dual-Vdd
-
Jun
-
F. Li, Y. Lin, and L. He, "FPGA power reduction using configurable dual-Vdd," in Proc. Des. Autom. Conf., Jun. 2004, pp. 735-740.
-
(2004)
Proc. Des. Autom. Conf
, pp. 735-740
-
-
Li, F.1
Lin, Y.2
He, L.3
-
11
-
-
20344368243
-
A dual-Vdd low power FPGA architecture
-
Aug
-
A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and T. Tuan, "A dual-Vdd low power FPGA architecture," in Proc. Int. Conf. Field-Programmable Logic and Appl., Aug. 2004, pp. 145-147.
-
(2004)
Proc. Int. Conf. Field-Programmable Logic and Appl
, pp. 145-147
-
-
Gayasen, A.1
Lee, K.2
Vijaykrishnan, N.3
Kandemir, M.4
Irwin, M.J.5
Tuan, T.6
-
13
-
-
84861427071
-
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
-
Jan
-
F. Li, Y. Lin, and L. He, "Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction," in Proc. Asia South Pacific Des. Autom. Conf., Jan. 2005, pp. 645-650.
-
(2005)
Proc. Asia South Pacific Des. Autom. Conf
, pp. 645-650
-
-
Li, F.1
Lin, Y.2
He, L.3
-
14
-
-
20344369312
-
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
-
Feb
-
Y. Lin, F. Li, and L. He, "Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2005, pp. 199-207.
-
(2005)
Proc. ACM Int. Symp. Field-Programmable Gate Arrays
, pp. 199-207
-
-
Lin, Y.1
Li, F.2
He, L.3
-
15
-
-
27944473343
-
Leakage efficient chip level dual-Vdd assignment with time slack allocation for FPGA power reduction
-
Jun
-
Y. Lin and L. He, "Leakage efficient chip level dual-Vdd assignment with time slack allocation for FPGA power reduction," in Proc. Des. Autom. Conf., Jun. 2005, pp. 720-725.
-
(2005)
Proc. Des. Autom. Conf
, pp. 720-725
-
-
Lin, Y.1
He, L.2
-
16
-
-
2442480635
-
Low power technology mapping for FPGA architectures with dual supply voltages
-
Feb
-
D. Chen, J. Cong, F. Li, and L. He, "Low power technology mapping for FPGA architectures with dual supply voltages," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2004, pp. 109-117.
-
(2004)
Proc. ACM Int. Symp. Field-Programmable Gate Arrays
, pp. 109-117
-
-
Chen, D.1
Cong, J.2
Li, F.3
He, L.4
-
17
-
-
84932115488
-
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
-
Aug
-
D. Chen and J. Cong, "Delay optimal low-power circuit clustering for FPGAs with dual supply voltages," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Aug. 2004, pp. 70-73.
-
(2004)
Proc. ACM Int. Symp. Field-Programmable Gate Arrays
, pp. 70-73
-
-
Chen, D.1
Cong, J.2
-
18
-
-
0003793410
-
-
Norwell, MA: Kluwer, Feb
-
V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs. Norwell, MA: Kluwer, Feb. 1999.
-
(1999)
Architecture and CAD for Deep-Submicron FPGAs
-
-
Betz, V.1
Rose, J.2
Marquardt, A.3
-
19
-
-
0002355759
-
A detailed router for allocating wire segments in field-programmable gate arrays
-
Apr
-
G. G. Lemieux and S. D. Brown, "A detailed router for allocating wire segments in field-programmable gate arrays," in Proc. ACM Phys. Des. Workshop, Apr. 1993, pp. 215-226.
-
(1993)
Proc. ACM Phys. Des. Workshop
, pp. 215-226
-
-
Lemieux, G.G.1
Brown, S.D.2
-
21
-
-
0031639695
-
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
-
Jun
-
J. Kao, S. Narendra, and A. Chandrakasan, "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns," in Proc. Des. Autom. Conf., Jun. 1998, pp. 495-500.
-
(1998)
Proc. Des. Autom. Conf
, pp. 495-500
-
-
Kao, J.1
Narendra, S.2
Chandrakasan, A.3
-
22
-
-
14244267091
-
-
U. of Berkeley Device Group, Online, Available
-
U. of Berkeley Device Group, Berkeley Predictive Technology Model, 2002. [Online], Available: http://www-device.eecs.berkeley.edu/ptm/mosfet.html
-
(2002)
Berkeley Predictive Technology Model
-
-
-
23
-
-
0034135572
-
Estimation for maximum instantaneous current through supply lines for CMOS circuits
-
Feb
-
Y.-M. Jiang, A. Krstic, and K.-T. Cheng, "Estimation for maximum instantaneous current through supply lines for CMOS circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 1, pp. 61-73, Feb. 2000.
-
(2000)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.8
, Issue.1
, pp. 61-73
-
-
Jiang, Y.-M.1
Krstic, A.2
Cheng, K.-T.3
-
24
-
-
0032022688
-
Automated low-power technique exploiting multiple supply voltages applied to a media processor
-
Mar
-
K. Usami et al., "Automated low-power technique exploiting multiple supply voltages applied to a media processor," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 463-472, Mar. 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, Issue.3
, pp. 463-472
-
-
Usami, K.1
-
26
-
-
0031634512
-
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme
-
M. Hamada et al., "A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme," in Proc. IEEE Custom Integr. Circuits Conf., 1998, pp. 495-498.
-
(1998)
Proc. IEEE Custom Integr. Circuits Conf
, pp. 495-498
-
-
Hamada, M.1
-
27
-
-
1542269352
-
Level conversion for dual-supply systems
-
F. Ishihara, F. Sheikh, and B. Nikolic, "Level conversion for dual-supply systems," in Proc. Int. Symp. Low Power Electron. and Des., 2003, pp. 164-167.
-
(2003)
Proc. Int. Symp. Low Power Electron. and Des
, pp. 164-167
-
-
Ishihara, F.1
Sheikh, F.2
Nikolic, B.3
-
28
-
-
0042635592
-
Pushing ASIC performance in a power envelope
-
R. Puri, L. Stok, J. Cohn, D. Kung, D. Pan, D. Sylvester, A. Srivastava, and S. Kulkarni, "Pushing ASIC performance in a power envelope," in Proc. Des. Autom. Conf., 2003, pp. 788-793.
-
(2003)
Proc. Des. Autom. Conf
, pp. 788-793
-
-
Puri, R.1
Stok, L.2
Cohn, J.3
Kung, D.4
Pan, D.5
Sylvester, D.6
Srivastava, A.7
Kulkarni, S.8
-
29
-
-
0022231945
-
TILOS: A posynomial programming approach to transistor sizing
-
J. P. Fishburn and A. E. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," in Proc. Int. Conf. Comput.-Aided Des., 1985, pp. 326-328.
-
(1985)
Proc. Int. Conf. Comput.-Aided Des
, pp. 326-328
-
-
Fishburn, J.P.1
Dunlop, A.E.2
-
30
-
-
0036916414
-
Methods for true power minimization
-
R. W. Brodersen, M. A. Horowitz, D. Markovic, B. Nikolic, and V. Stojanovic, "Methods for true power minimization," in Proc. Int. Conf. Comput.-Aided Des., 2002, pp. 35-42.
-
(2002)
Proc. Int. Conf. Comput.-Aided Des
, pp. 35-42
-
-
Brodersen, R.W.1
Horowitz, M.A.2
Markovic, D.3
Nikolic, B.4
Stojanovic, V.5
-
31
-
-
0004907582
-
-
MCNC, Research Triangle Park, NC
-
MCNC Designers' Manual, MCNC, Research Triangle Park, NC, 1993.
-
(1993)
MCNC Designers' Manual
-
-
-
32
-
-
0003647211
-
-
Microelectronics Center North Carolina, Research Triangle Park, NC, Tech. Rep
-
S. Yang, "Logic synthesis and optimization benchmarks," Microelectronics Center North Carolina, Research Triangle Park, NC, Tech. Rep., 1991.
-
(1991)
Logic synthesis and optimization benchmarks
-
-
Yang, S.1
-
33
-
-
33947601853
-
-
International Technology Roadmap for Semiconductors, Online, Available
-
International Technology Roadmap for Semiconductors, 2003. [Online]. Available: http://public.itrs.net/Files/2003ITRS/Home2003.htm
-
(2003)
-
-
-
34
-
-
27844495094
-
Circuits and architectures for field programmable gate array with configurable supply voltage
-
Sep
-
Y. Lin, F. Li, and L. He, "Circuits and architectures for field programmable gate array with configurable supply voltage," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 9, pp. 1035-1047, Sep. 2005.
-
(2005)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.13
, Issue.9
, pp. 1035-1047
-
-
Lin, Y.1
Li, F.2
He, L.3
-
35
-
-
27944473343
-
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
-
Jun
-
Y. Lin and L. He, "Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction," in Proc. Des. Autom. Conf., Jun. 2005, pp. 720-725.
-
(2005)
Proc. Des. Autom. Conf
, pp. 720-725
-
-
Lin, Y.1
He, L.2
|