A flexible power model for FPGAs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 312-321

  Poon, Kara K W ^a   Yan, Andy ^a   Wilton, Steven J E ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE ARCHITECTURES;

CAD FLOW; CAD TOOL; FPGA ARCHITECTURES; LEAKAGE POWER; MODEL ESTIMATES; OPTIMIZATION GOALS; POWER MODEL; RESEARCH COMMUNITIES;

COMPUTER AIDED LOGIC DESIGN;

EID: 50949100112     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46117-5_33     Document Type: Conference Paper

References (20)

1. The International Technology Roadmap for Semiconductors, 2001 Edition, International Sematech, Austin, Texas, 2001.
2. A. Allan, D. Edenfeld, W. Joyner Jr, A. Khang, M. Rogers, Y. Zorian: "2001 Technology Roadmap for Semiconductors". Computer, Vol. 35, Issue 1, Jan 2002, pp. 42-53 (Pubitemid 34069380)
3. G. Lim, R. Saleh, "Trends in Low Power Digital Systems on Chip Design", in International Symposium on Quality of Electronic Design, March 2002.
4. V. George, H. Zhang, J. Rabaey, "The design of a low energy FPGA", in proceedings of the Low Power Electronics and Design, August 1999.
5. L. Shang, A. S. Kaviani, K. Bathala, "Dynamic Power Consumption in Virtex-II FPGA Family", ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 2002.
6. F. G. Wolff, M. J. Knieser, D. J. Weyer, C. A. Papachristou, "High-level low power FPGA design methodology" National Aerospace and Electronics Conference, October 2000.
7. A. Garcia, W. Burleson, J. Danger, "Power Modelling in Field Programmable Gate Arrays (FPGA)", in Proceeding of Field-Programmable Logic and Applications, pp. 396-404, September 1999.
8. L. Shang, N. K. Jha, "High-level power modeling of CPLDs and FPGAs", International Conference on Computer Design, September 2001.
9. K. Roy, "Power-Dissipation Driven FPGA Place and Route Under Timing Constraints", IEEE Transactions on Circuits and Systems: Fundamental Theory and Applications, Vol 46, No 5 May 1999
10. V. Betz, Architectures and CAD for Speed and Area Optimizations of FPGAs. PhD thesis, University of Toronto, 1998.
11. V. Betz, VPR and T-VPack User's Manual. version 4.30, March 2000.
12. F. N. Najm, "A Survey of Power Estimation Techniques in VLSI Circuits", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol 2, No 4, pp 446-455, December 1994.
13. G. Yeap, Practical Low Power Digital VLSI Design. Kluwer Academic Publishers, 1998
14. S. J. E. Wilton, N. P. Jouppi, "CACTI: An Enhanced Cache Access and Cycle Time Model", in IEEE Journal of Solid-State Circuits, Vol 31, No 5, pp 677-687, May 1996. (Pubitemid 126561504)
15. D. Eckerbert, P.L. Edefors, "Interconnect-Driven Short-Circuit Power Modeling", in Proceedings of Euromicro Symposium on Digital Systems, September 2001.
16. Altera. APEX 20K Programmable Logic Device Family Data Sheet. version 4.1. Altera Corporation. September 2001.
17. Xilinx. Virtex-E 1.8V Field Programmable Gate Arrays Data Sheet. version 2.2. Xilinx Corporation. November 2001.
18. S.M. Kang, Y. Leblebici, CMOS Digital Integated Circuits: Analysis and Design. 1999
19. M. I. Masud, S. J. E. Wilton, "A New Switch Block for Segmented FPGAs", in Proceeding of Field-Programmable Logic and Applications, pp. 396-404, September 1999.
20. K.Y. Toh, P.K. Ko, R.G. Meyer, "An Engineering Model for Short-Channel MOS Devices", IEEE Journal of Solid-State Circuits, Vol. 23, No. 4, August 1988.