Estimation for maximum instantaneous current through supply lines for CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 1, 2000, Pages 61-73

  Jiang, Yi Min ^a,b   Krstic, Angela ^a,c   Cheng, Kwang Ting ^a,c  

^a IEEE

^b SYNOPSYS INC   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; GENETIC ALGORITHMS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; PROBABILITY;

MAXIMUM INSTANTANEOUS CURRENT;

VLSI CIRCUITS;

EID: 0034135572     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.820762     Document Type: Article

References (16)

1. S. Chowdhury and J. S. Barkatullah, "Estimation of maximum current in MOS IC logic circuits," IEEE Trans. Computer-Aided Design, pp. 642-654, June 1990.
2. J. Cong, Z. Li, and R. Bagrodia, "Acyclic multi-way partitioning of Boolean networks," in Proc. Design Automation Conf., June 1994, pp. 670-675.
3. S. Devadas, K. Keutzer, and S. Malik, "Computation of floating mode delay in combinational circuits: Theory and algorithms," IEEE Trans. Computer-Aided Design, pp. 1913-1923, Dec. 1993.
4. S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation," IEEE Trans. Computer-Aided Design, pp. 373-383, Mar. 1992.
5. D. E. Goldberg and R. Burch, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading, MA: Addison-Wesley, 1989.
6. M. S. Hsiao, E. M. Rudnick, and J. H. Patel, "K2: An estimator for peak sustainable power of VLSI circuits," in Int. Symp. Low-Power Electronics and Design (ISLPED), Aug. 1997, pp. 178-183.
7. Y.-M. Jiang, K.-T. Cheng, and A. Krstic, "Estimation of maximum power and instantaneous current using a genetic algorithm," in Proc. IEEE Custom Integrated Circuits Conf, May 1997, pp. 135-138.
8. Y.-M. Jiang and K.-T. Cheng, "Exact and approximate estimation for maximum instantaneous current of CMOS circuits," in Proc. DATE'98, Feb. 1998, pp. 698-702.
9. A. Krstic and K.-T. Cheng, "Vector generation for maximum instantaneous current through supply lines for CMOS circuits," in Proc. Design Automation Conf., June 1997, pp. 383-388.
10. H. Kriplani, F. N. Najm, and I. N. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution," IEEE Trans. Computer-Aided Design, pp. 998-1012, Aug. 1995.
11. User's Manual, LINDO Systems, Inc., 1996.
12. B. L. Miller and D. E. Goldberg, "Genetic algorithms, tournament selection, and the effects of noise," Complex Syst., pp. 193-212, June 1995.
13. PowerMill Reference Manual, Aug. 1998.
14. C.-Y. Wang and K. Roy, "Maximum power estimation for CMOS circuits using deterministic and statistic approaches," in Proc. 9th Int. Conf. VLSI Design, Jan. 1995, pp. 364-369.
15. C.-Y. Wang, K. Roy, and T.-L. Chou, "Maximum power estimation for sequential circuits using a test generation based technique," in Proc. IEEE Custom Integrated Circuits Conf, Apr. 1996, pp. 229-232.
16. C.-Y. Wang and K. Roy, "Estimation of maximum power for sequential circuits considering spurious transitions," in Proc. ICCD, 1997, pp. 746-751.