Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 720-725

  Lin, Yan ^a   He, Lei ^a  

^a Engineering IV   (United States)

Author keywords

FPGA; Low power; Programmable Vdd; Time slack

Indexed keywords

BENCHMARKING; HEURISTIC METHODS; RESOURCE ALLOCATION;

LOW POWER; PROGRAMMABLE-VDD; TIME SLACK;

MICROPROCESSOR CHIPS;

EID: 27944473343     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065579.1065769     Document Type: Conference Paper

References (13)

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