Reducing leakage energy in FPGAs using region-constrained placement

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn 12, Issue , 2004, Pages 51-58

  Gayasen, A ^a   Tsai, Y ^a   Vijaykrishnan, N ^a   Kandemir, M ^a   Irwirn, M J ^a   Tuan, T ^b  

^a The Center for Nanotechnology Education and Utilization   (United States)

^b XILINX INC   (United States)

Author keywords

FPGA; Leakage power; Region constrained placement

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; CONSTRAINT THEORY; GATES (TRANSISTOR); LEAKAGE CURRENTS; OPTIMIZATION;

LEAKAGE POWER; LEAKAGE POWER CONSUMPTION; POWER OPTIMIZATION; REGION CONSTRAINED PLACEMENT;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 2442474225     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/968280.968289     Document Type: Conference Paper

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