Circuits and architectures for field programmable gate array with configurable supply voltage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 9, 2005, Pages 1035-1047

  Lin, Yan ^a,b   Li, Fei ^a,b   He, Lei ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Digital integrated circuits; Field programmable gate arrays (FPGAs); Power supplies

Indexed keywords

POWER SUPPLIES; PROGRAMMABILITY; SRAM CELLS; SUPPLY VOLTAGE;

CIRCUIT THEORY; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; ENERGY EFFICIENCY; SWITCHES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 27844495094     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.857180     Document Type: Conference Paper

References (33)

1. E. Kusse and J. Rabaey, "Low-energy embedded FPGA structures," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 1998, pp. 155-160.
2. K. Poon, A. Yan, and S. Wilton, "A flexible power model for FPGAs," in Proc. 12th Int. Conf. on Field-Programmable Logic and Applications, Sep. 2002.
3. F. Li, D. Chen, L. He, and J. Cong, "Architecture evaluation for power-efficient FPGAs," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2003.
4. F. Li and L. He, "Power modeling and characteristics of field programmable gate arrays," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., Oct. 2005.
5. T. Tuan and B. Lai, "Leakage power analysis of a 90 nm FPGA," in Proc. IEEE Custom Integrated Circuits Conf., 2003.
6. J. H. Anderson, F. N. Najm, and T. Tuan, "Active leakage power optimization for FPGAs," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2004.
7. J. Lamoureux and S. J. Wilton, "On the interaction between power-aware FPGA CAD algorithms," in Proc. Int. Conf. Computer-Aided Design, Nov. 2003, pp. 701-708.
8. A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and T. Tuan, "Reducing leakage energy in FPGA s using region-constrained placement," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2004.
9. Y. Lin, F. Li, and L. He, "Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction," in Proc. Asia South Pacific Design Automation Conf., Jan. 2005.
10. F. Li, Y. Lin, L. He, and J. Cong, "Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2004.
11. F. Li, Y. Lin, and L. He, "FPGA power reduction using configurable dual-vdd," in Proc. Design Automation Conf., Jun. 2004.
12. _, "Vdd programmability to reduce fpga interconnect power," in Proc. Int. Conf. Computer-Aided Design, Nov. 2004.
13. J. H. Anderson and F. N. Najm, "Low-power programmable routing circuitry for FPGAs," in Proc. Int. Conf. Computer-Aided Design, Nov. 2004.
14. A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and T. Tuan, "A dual-vdd low power FPGA architecture," in Proc. Int. Conf. Field-Programmable Logic and its Application, Aug. 2004.
15. J. Rose, R. Francis, D. Lewis, and P. Chow, "Architecture of field-programmable gate arrays: The effect of logic functionality on area efficiency," IEEE J. Solid-State Circuits, 1990.
16. S. Singh, J. Rose, P. Chow, and D. Lewis, "The effect of logic block architecture on FPGA performance," IEEE J. Solid-State Circuits, 1992.
17. E. Ahmed and J. Rose, "The effect of LUT and cluster size on deep-submicron FPGA performance and density," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2000, pp. 3-12.
18. Y. Lin, F. Li, and L. He, "Power modeling and architecture evaluation for FPGA with novel circuits for vdd programmability," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2005.
19. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs: Kluwer Academic Publishers, 1999.
20. G. G. Lemieux and S. D. Brown, "A detailed router for allocating wire segments in field-programmable gate arrays," in Proc. ACM Physical Design Workshop, Apr. 1993.
21. D. Lewis et al., "The stratix routing and logic architecture," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2003.
22. (2002) Predictive Technology Model. Univ. of Berkeley Device Group. [Online]. Available: http://www.device.eecs.berkeley.edu/ptm/mosfet.html
23. (2002) International Technology Roadmap for Semiconductor. [Online]. Available: http://public.itrs.net/
24. S. Yang, "Logic Synthesis and Optimization Benchmarks, Version 3.0," Microelectronics Center of North Carolina (MCNC), 1991.
25. "Virtex-II 1.5 v Platform FPGA Complete Data Sheet," Xilinx Corporation, 2002.
26. D. E. Lackey et al., "Managing power and performance for system-on-chip designs using voltage islands," in Proc. Int. Conf. Computer-Aided Design, 2002, pp. 195-202.
27. K. Usami and M. Horowitz, "Clustered voltage scaling techniques for low-power design," in Proc. Int. Symp. Low Power Electronics and Design, 1995.
28. C. Chen, A. Srivastava, and M. Sarrafzadeh, "On gate level power optimization using dual-supply voltages," IEEE Trans. on VLSI Systems, vol. 9, pp. 616-629, Oct. 2001.
29. M. Hamada, Y. Ootaguro, and T. Kuroda, "Utilizing surplus timing for power reduction," in Proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 89-92.
30. B. Calhoun, F. Honore, and A. Chandrakasan, "Design methodology for fine-grained leakage control in MTCMOS," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 2003.
31. M. Hamada et al., "A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme," in Proc. IEEE Custom Integrated Circuits Conf., 1998, pp. 495-498.
32. L. Cheng, P. Wong, F. Li, Y. Lin, and L. He, "Device and architecture co-optimization for FPGA power reduction," in Proc. Design Automation Conf., Jun. 2005.
33. D. Lewis et al., "The stratix II routing and logic architecture," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Feb. 2005.