An industry perspective on current and future state of the art in system-on-chip (SoC) technology

Proceedings of the IEEE

Volumn 94, Issue 6, 2006, Pages 1121-1137

  Claasen, Theo A C M ^a,b  

^a IEEE   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Complimentary metal oxide semiconductor; Embedded systems; Integrated circuit design; Integrated circuit process technology; Ip reuse; System in package (SiP); System on chip (SoC)

Indexed keywords

EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; SCALING LAWS; SUBMILLIMETER WAVES; SYSTEMS ANALYSIS;

COMPLIMENTARY METAL-OXIDE-SEMICONDUCTOR; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT PROCESS TECHNOLOGY; IP REUSE; SYSTEM-IN-PACKAGE (SIP); SYSTEM-ON-CHIP (SOC);

ELECTRONICS INDUSTRY;

EID: 33947377467     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2006.873616     Document Type: Article

References (38)

1. G. Moore, "Cramming more components onto integrated circuits," Electron. Mag., vol. 38, no. 8, pp. 114-117, Apr. 19, 1965.
2. G. E. Moore, "Lithography and the future of Moore's law," Proc. SPIE: Optical/Laser Microlithography VIII, vol. 2440, pp. 2-17, Feb. 20, 1995.
3. R. R. Schaller, "Moore's law: Past, present, and future," IEEE Spectr., pp. 52-59, Jun. 1997.
4. International Technology Roadmap for Semiconductors (ITRS). [Online]. Available: http://public.itrs.net/
5. R. Perez, "Controlling EMI in telecommunications ICS," Proc. 2002 IEEE Int. Symp. Electromagnetic Compatibility, vol. 1, pp. 345-349.
6. C. M. Osburn, I. Kim, S. K. Han, I. De et al., "Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?" IBM J. Res. Develop., vol. 46, no. 2/3, Mar./May 2002.
7. F. Boeuf et al., "A conventional 45 nm CMOS node low-cost platform for general purpose and low power applications," Proc. IEEE Int. Electron Devices Meeting, 2004, pp. 425-428.
8. E. J. Nowak, T. Ludwig, I. Aller, J. Kedzierski, M. Leong, B. Rainey, M. Breitwisch, V. Gemhoefer, J. Keinert, and D. M. Fried, "Scaling beyond the 65 nm node with FinFET-DGCMOS," Proc. IEEE 2003 Custom Integrated Circuits Conf., pp. 339-342.
9. G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, "Review on high-k dielectrics reliability issues," IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 5-19, Mar. 2005.
10. P. Stolk, "New gate stack solutions for CMOS technologies from a European perspective," presented at the 7th Annu. Int. Forum Semiconductor Technology, Paris, France, 2004.
11. D. Aimé et al., "Work function tuning through dopant scanning and related effects Ni fully suicided gate for sub-45 nm nodes CMOS," Proc. IEEE Int. Electron Devices Meeting, 2004, pp. 87-90.
12. E. J. Nowak, T. Ludwig, I. Aller, J. Kedzierski, M. Leong, B. Rainey, M. Breitwisch, V. Gemhoefer, J. Keinert, and D. M. Fried, "Scaling beyond the 65 nm node with FinFET-DGCMOS," Proc. IEEE 2003 Custom Integrated Circuits Conf., pp. 339-342.
13. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," Tech. Dig. Int. Electron Devices Meeting 2002 (IEDM '02), pp. 251-254.
14. T. Nirschl, P.-F. Wang, C. Weber, J. Sedlmeir, R. Heinrich, R. Kakoschke, K. Schrufer, J. Holz, C. Pacha, T. Schulz, M. Ostermayr, A. Olbrich, G. Georgakos, E. Ruderer, W. Hansch, and D. Schmitt-Landsiedel, "The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes," Tech. Dig. IEEE Int. Electron Devices Meeting 2004 (IEDM'04), pp. 195-198.
15. R. Binner, A. Schopper, and J. Castaneda, "Gold wire bonding on low-K material: A new challenge for interconnection technology," Proc. IEEE/CPMT/SEMI 29th Int. Electronics Manufacturing Technology Symp. 2004, pp. 13-17.
16. C. C. Yeh, W. J. Tsai, T. C. Lu, Y. Y. Liao, N. K. Zous, H. Y. Chen, T. Wang, W. Ting, J. Ku, and C.-Y. Lu, "Reliability and device scaling challenges of trapping charge flash memories," Proc. 11th Int. Symp. Physical and Failure Analysis of Integrated Circuits 2004 (IPFA 2004), pp. 247-250.
17. R. von Vignau, "Advances in SoC design push abstraction," Electron. Weekly, Sep. 16, 2005.
18. R. Radojcic and M. Rencher. (2005, Nov.). "Old rules no longer apply," EETimes (Special Report). [Online]. Available: http://img.cmpnet.com/eedesign/2003/inside_eedesign5.pdf
19. T. Waayers, "An improved test control architecture and test control expansion for core-based system chips," Proc. IEEE Int. Test Conf., 2003, pp. 1145-1154.
20. E. J. Marinisscn, "The role of test protocols in automated test generation for embedded-core-based system ICs," J. Electron. Testing Theory Appl. (JETTA), vol. 18, no. 4/5, pp. 435-454, Aug. 2002.
21. E. J. Marinissen et al., "A structured and scalable mechanism for test access to embedded reusable cores," Proc. IEEE Int. Test Conf. (ITC'98), pp. 284-293.
22. _, "On IEEE P1500's standard for embedded core test," J. Electron. Testing Theory Appl. (JETTA), vol. 18, no. 4/5, pp. 365-383, Aug. 2002.
23. S. K. Goel and E. J. Marinissen, "SOC test architecture design for efficient utilization of test bandwidth," ACM Trans. Des. Automat. Electron. Syst., vol. 8, no. 4, pp. 399-429, Oct. 2003.
24. U. Ingelsson, S. K. Goel, E. Larsson, and E. J. Marinissen, "Test scheduling for modular SOC's in an abort-on-fail environment," Proc. IEEE Eur. Test Symp. (ETS'05), pp. 8-13.
25. J. Rajski et al. "Embedded deterministic test for low cost manufacturing test," Proc. IEEE Int. Test Conf. (ITC), 2002, pp. 301-310.
26. F. Poehl et al., "Industrial experience with adoption of EDT for low-cost test without concessions," Proc. IEEE Int. Test Conf. (ITC), 2003, pp. 1211-1220.
27. M. Sgroi et al., "Addressing the system-on-a-chip interconnect woes through communication-based design," Proc. Design Automation Conf. (DAC), 2001, pp. 667-672.
28. D. M. Chapiro, "Globally-asynchronous locally-synchronous systems," Ph.D. dissertation, Stanford Univ., Stanford, CA, Oct. 1984.
29. A. Chattopadhyay and Z. Zilic, "GALDS: A complete framework for designing multiclock ASIC's and SoCs," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 641-654, Jun. 2005.
30. S. Bhunia, A. Datta, N. Banerjee, and K. Roy, "GAARP: A power-aware GALS architecture for real-time algorithm-specific tasks," IEEE Trans. Comput., vol. 54, no. 6, pp. 752-766, Jun. 2005.
31. K. Goossens et al., "Interconnect and memory organization in SOC's for advanced set-top boxes and TV - evolution, analysis, and trends," in Interconnect-Centric Design for Advanced SoC and NoC. Norwell, MA: Kluwer, 2004, pp. 399-423.
32. _, "The aethereal network on chip: Concepts, architectures, and implementations," IEEE Des. Test Comput., vol. 22, no. 5, pp. 21-31, Sep./Oct. 2005.
33. E. Rijpkema et al., "Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip," IEE Proc. Comput. Dig. Tech., vol. 150, no. 5, pp. 294-302, Sep. 2003.
34. J. Leijten, G. Burns, J. Huisken, E. Waterlander, and A. van Wel, "AVISPA: a massively parallel reconfigurable accelerator," Proc. Int. Symp. System-on-Chip 2003, pp. 165-168.
35. K. Goossens et al., "A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification," Proc. Design, Automation and Test in Europe Conf., and Exhibition (DATE), 2005, pp. 1182-1187.
36. R. Leupers, "Compiler design issues for embedded processors," IEEE Des. Test Comput., vol. 19, no. 4, pp. 51-58, Jul./Aug. 2002.
37. N. Tanaka, Y. Yoshimira, T. Naito, C. Miyazaki, Y. Nemoto, M. Nakanishi, and T. Akazawa, "Ultra-thin 3D-stacked SIP formed using room-temperature bonding between stacked chips," Proc. Electronic Components and Technology (ECTC '05), pp. 788-794.
38. W.-C. Lo, Y.-H. Chen, J.-D. Ko, T.-Y. Kuo, C.-W. Chien, Y.-C. Chen, W.-Y. Chen, F.-J. Leu, and H.-T. Hu, "Development and characterization of low cost ultrathin 3-D interconnect," Proc. Electronic Components and Technology (ECTC '05), pp. 337-342.