Ultra-thin 3D-stacked SIP formed using room-temperature bonding between stacked chips

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2005, Pages 788-794

  Tanaka, Naotaka ^a   Yoshimira, Yoshihiro ^a   Naito, Takahiro ^b   Miyazaki, Chuichi ^b   Nemoto, Yoshihiko ^b   Nakanishi, Masaki ^b   Akazawa, Takashi ^b  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; CHEMICAL VAPOR DEPOSITION; ELECTRODES; GOLD; RANDOM ACCESS STORAGE; SILICON WAFERS; SUBSTRATES;

ELECTRICAL INTERCONNECTION; MICRO PROCESSING; SDRAM;

MICROPROCESSOR CHIPS;

EID: 22544481114     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. K. Koyanagi, "Future System-on-Silicon LSI Chip", IEEE Micro, Vol. 18, No. 4, 1988, pp. 17-22.
2. th Ann. Int. KGD Packaging and Test Workshop, 2000, pp. 336-352.
3. th Electronic Components and Technology Conf, 2000, pp. 702-705.
4. th Electronic Components and Technology Conf, 2002.
5. Y. Sogawa, T. Yamazaki, I. Hazeyama and S. Kitajo, "Reliability of an Ultra-high-density 3-dimensional-stacked Package "FFCSP"", Proc. of International Conference on Electronics Packaging, Japan, Apr. 2004, pp. 41-46.