Impacts of gate structure on dynamic threshold SOI nMOSFETs

IEEE Electron Device Letters

Volumn 23, Issue 8, 2002, Pages 497-499

  Lo, Wen Cheng ^b   Chang, Sun Jay ^b   Chang, Chun Yen ^a,b   Chao, Tien Sheng ^b,c  

^a IEEE

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

Dynamic threshold MOS (DTMOS); H gate; Silicon on insulator (SOI); T gate

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC PROPERTIES; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

DRAIN-INDUCED-BARRIER-LOWERING (DIBL);

MOSFET DEVICES;

EID: 0036686922     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2002.801334     Document Type: Article

References (10)

1. A through investigation of the degradation induced by hot-carrier injection in deep submicron N- and P-channel partially and fully depleted unibond and SIMOX MOSFETs
2. Instability study of partially depleted SOI-MOSFET due to floating body effect using high energy nuclear microprobes
3. Reduced reverse narrow channel effect in thin SOI nMOSFETs
4. An SOI voltage-controlled bipolar-MOS device
5. Voltage controlled bipolar-MOS ring oscillator
6. Analysis of hybrid-mode operation of SOI MOSFETs
7. 1 V high-speed digital circuit technology with 0.5 μm multi-threshold CMOS
8. A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation