PD/SOI SRAM performance in presence of gate-to-body tunneling current

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 6, 2003, Pages 1106-1113

  Joshi, Rajiv V ^a   Chuang, Ching Te ^a   Fung, Samuel K H ^b   Assaderaghi, Fari ^b   Sherony, Melanie ^b   Yang, I ^b   Shahidi, G ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM RESEARCH   (United States)

Author keywords

Gate to body tunneling (PD SOI); Parasitic bipolar current; Partially depleted silicon on insulator (PD SOI); SRAM read performance; Write performance

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRON TUNNELING; LOW TEMPERATURE OPERATIONS; MOSFET DEVICES; PERFORMANCE; SILICON ON INSULATOR TECHNOLOGY;

GATE-TO-BODY TUNNELING; PARASITIC BIPOLAR CURRENT; PARTIALLY DEPLETED SILICON-ON-INSULATOR CMOS STATIC RANDOM ACCESS MEMORY; READ PERFORMANCE; WRITE PERFORMANCE;

STATIC RANDOM ACCESS STORAGE;

EID: 0742321604     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.817552     Document Type: Article

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