Supply-voltage optimization for below-70-nm technology-node MOSFETs

IEEE Transactions on Semiconductor Manufacturing

Volumn 15, Issue 2, 2002, Pages 151-156

  Wakabayashi, Hitoshi ^a,b,c   Samudra, Ganesh Shankar ^a,b,d   Djomehri, Ihsan J ^b   Nayfeh, Hasan ^a,b   Antoniadis, Dimitri A ^a,b  

^a IEEE   (Japan)

^b Massachusetts Institute of Technology Cambridge   (United States)

^c NEC CORPORATION   (Japan)

^d NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

CMOS; Energy delay product; Gate delay; Power consumption; Power supply voltage; Short channel effect

Indexed keywords

ENERGY-DELAY PRODUCTS; GATE DELAYS; SHORT-CHANNEL EFFECTS (SCE);

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC POWER UTILIZATION; GATES (TRANSISTOR); LITHOGRAPHY; LSI CIRCUITS; OPTIMIZATION; POLYSILICON; POWER CONTROL; VOLTAGE CONTROL;

MOSFET DEVICES;

EID: 0036565615     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.999586     Document Type: Article

References (8)

1. 25 nm CMOS design considerations
2. 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays
3. 45-nm gate length CMOS technology and beyond using steep halo
4. 15 nm gate length planar CMOS transistor
5. Device scaling limits of Si MOSFET's and their application dependencies
6. A 1.2 V, 0.1 μm gate length CMOS technology: Design and process issues