45nm CMOS platform technology (CMOS6) with high density embedded memories

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 12-13

  Iwai, M ^a   Oishi, A ^a   Sanuki, T ^a   Takegawa, Y ^a   Komoda, T ^a   Morimasa, Y ^a   Ishimaru, K ^b   Takayanagi, M ^b   Eguchi, K ^c   Matsushita, D ^c   Muraoka, K ^d   Sunouchi, K ^a   Noguchi, T ^a  

^a System LSI Division   (Japan)

^b SoC Research and Development Center   (Japan)

^c Proc and Mfg Engineering Center   (Japan)

^d TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; DIELECTRIC DEVICES; ENERGY UTILIZATION; INDUCTANCE; LEAKAGE CURRENTS; OPTIMIZATION; TRANSMISSION ELECTRON MICROSCOPY;

PLASMA NITRIDATION; POWER CONSUMPTION; SLIMMING PROCESS;

CMOS INTEGRATED CIRCUITS;

EID: 4544377579     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345364     Document Type: Conference Paper

References (4)

1. K.Sekine et al. IEDM Tech. Dig. 2003, p. 103.
2. D.Matsushita et al., submitted to 2004 VLSI Symp.
3. N.Yananagiya et al. IEDM Tech. Dig. 2002, p.57.
4. J A.Davis et.al, IEEE Trans. Electron Devices, vol. ED-45, 1998, p.580