45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for Low-Operation-Power (LOP) applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 52-55

  Okuno, M ^a   Okabe, K ^b   Sakuma, T ^b   Suzuki, K ^b   Miyashita, T ^a   Yao, T ^b   Morioka, H ^b   Terahara, M ^b   Kojima, Y ^b   Watatani, H ^b   Sugimoto, K ^b   Watanabe, T ^b   Hayami, Y ^b   Mori, T ^b   Kubo, T ^b   Iba, Y ^b   Sugiura, I ^b   Fukutome, H ^a   Morisaki, Y ^a   Minakata, H ^a   Ikeda, K ^a   Kishii, S ^a   Shimizu, N ^a   Tanaka, T ^a   Asai, S ^b   Nakaishi, M ^b   Fukuyama, S ^b   Tsukune, A ^b   Yamabe, M ^a   Hanyuu, I ^b   Miyajima, M ^b   Kase, M ^b   Watanabe, K ^b   Satoh, S ^a   Sugii, T ^a   more..

^a FUJITSU LABORATORIES LTD   (Japan)

^b NONE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LOW OPERATION POWER (LOP) APPLICATIONS; MIDDLE ETCH STOPPER (MES); NANO CLUSTERING SILICA (NCS);

CAPACITANCE; ELECTRIC WIRE; ETCHING; NANOSTRUCTURED MATERIALS; SILICA; STATIC RANDOM ACCESS STORAGE;

CMOS INTEGRATED CIRCUITS;

EID: 33847715120     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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