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Volumn 2005, Issue , 2005, Pages 52-55
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45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for Low-Operation-Power (LOP) applications
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Author keywords
[No Author keywords available]
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Indexed keywords
LOW OPERATION POWER (LOP) APPLICATIONS;
MIDDLE ETCH STOPPER (MES);
NANO CLUSTERING SILICA (NCS);
CAPACITANCE;
ELECTRIC WIRE;
ETCHING;
NANOSTRUCTURED MATERIALS;
SILICA;
STATIC RANDOM ACCESS STORAGE;
CMOS INTEGRATED CIRCUITS;
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EID: 33847715120
PISSN: 01631918
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (6)
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References (8)
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