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Volumn 2005, Issue , 2005, Pages 52-55

45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for Low-Operation-Power (LOP) applications

Author keywords

[No Author keywords available]

Indexed keywords

LOW OPERATION POWER (LOP) APPLICATIONS; MIDDLE ETCH STOPPER (MES); NANO CLUSTERING SILICA (NCS);

EID: 33847715120     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (8)
  • 1
    • 84874215871 scopus 로고    scopus 로고
    • Digest of Symp
    • H.Fukutome et al., Digest of Symp. VLSI 2005, pp. 140-141.
    • (2005) VLSI , pp. 140-141
    • Fukutome, H.1
  • 4
    • 33847711254 scopus 로고    scopus 로고
    • Digest of Symp
    • F. Boeuf et al., Digest of Symp. VLSI 2005, pp. 130-131.
    • (2005) VLSI , pp. 130-131
    • Boeuf, F.1
  • 5
    • 33847714958 scopus 로고    scopus 로고
    • Digest of Symp
    • F. L. Yang et al., Digest of Symp. VLSI 2004, pp. 8-9.
    • (2004) VLSI , pp. 8-9
    • Yang, F.L.1
  • 7
    • 33847717324 scopus 로고    scopus 로고
    • I. Sugiura et al., Proceedings of IITC 2005, pp. 15-17.
    • I. Sugiura et al., Proceedings of IITC 2005, pp. 15-17.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.