A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation

IEEE Transactions on Electron Devices

Volumn 51, Issue 2, 2004, Pages 195-203

  Mui, Man Lung ^a   Banerjee, Kaustav ^b   Mehrotra, Amit ^a  

^a University of Illinois at Urbana Champaign   (United States)

^b University of California   (United States)

Author keywords

Bandwidth; Critical inductance; Delay per unit length; Global interconnect optimization; Interconnect power dissipation optimization; International technology roadmap for semiconductors (ITRS); Optimal buffering; Technology scaling

Indexed keywords

BANDWIDTH; CAPACITANCE; CMOS INTEGRATED CIRCUITS; INDUCTANCE; OPTIMIZATION;

NANOMETER; POWER DISSIPATION;

VLSI CIRCUITS;

EID: 0442295641     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.820651     Document Type: Article

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