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Volumn 2006, Issue , 2006, Pages 1147-1153

Design, fabrication and implementation of smart three axis compliant interconnects for ultra-thin chip stacking technology

Author keywords

[No Author keywords available]

Indexed keywords

PACKAGE SUBSTRATES; SMART THREE AXIS COMPLIANT (STAC) INTERCONNECTS; ULTRA THIN CHIP STACKING TECHNOLOGY; ULTRA THIN GLASS DIES;

EID: 33845579338     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645798     Document Type: Conference Paper
Times cited : (6)

References (24)
  • 1
    • 24644476549 scopus 로고    scopus 로고
    • Smart Three Axis Compliant (STAG) interconnect: An ultra-high density MEMS based interconnect for wafer-level ultra-thin die stacking technology
    • Orlando, FL, May.
    • th Electronic Components and Technology Conf, Orlando, FL, May. 2005, pp. 1089-1093.
    • (2005) th Electronic Components and Technology Conf , pp. 1089-1093
    • Arunasalam, P.1
  • 7
    • 0033336780 scopus 로고    scopus 로고
    • Processing thick multilevel polyimide films for 3-D stacked memory
    • Caterer, M. D. et al, "Processing Thick Multilevel Polyimide Films for 3-D Stacked Memory," IEEE Trans on Advanced Packaging, Vol. 22, No. 2 (1999), pp. 189-199.
    • (1999) IEEE Trans on Advanced Packaging , vol.22 , Issue.2 , pp. 189-199
    • Caterer, M.D.1
  • 8
    • 24644447011 scopus 로고    scopus 로고
    • Real chip size three-dimensional stacked package
    • Yamazaki, T. et al., "Real Chip Size Three-Dimensional Stacked Package," IEEE Trans on Advanced Packaging, Vol. 28, No. 3 (2005), pp. 397-403.
    • (2005) IEEE Trans on Advanced Packaging , vol.28 , Issue.3 , pp. 397-403
    • Yamazaki, T.1
  • 9
    • 0032116366 scopus 로고    scopus 로고
    • Future system-on-silicon LSI chips
    • Koyanagi, M. et al, "Future System-on-Silicon LSI Chips," IEEE Micro, Vol. 18, No. 4 (1998), pp. 17-22.
    • (1998) IEEE Micro , vol.18 , Issue.4 , pp. 17-22
    • Koyanagi, M.1
  • 10
    • 24644517630 scopus 로고    scopus 로고
    • Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias
    • Shaper, L. W. et al, "Architectural Implications and Process Development of 3-D VLSI Z-Axis Interconnects Using Through Silicon Vias," IEEE Trans on Advanced Packaging, Vol. 28, No. 3 (2005), pp. 356-366.
    • (2005) IEEE Trans on Advanced Packaging , vol.28 , Issue.3 , pp. 356-366
    • Shaper, L.W.1
  • 13
    • 0141940290 scopus 로고    scopus 로고
    • Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for Gigascale Integration (GSI)
    • Bakir, M. S. et al, "Sea of Leads (SoL) Ultrahigh Density Wafer-Level Chip Input/Output Interconnections for Gigascale Integration (GSI)," IEEE Trans on Electron Devices, Vol. 50, No. 10 (2003), pp 2039-2048.
    • (2003) IEEE Trans on Electron Devices , vol.50 , Issue.10 , pp. 2039-2048
    • Bakir, M.S.1
  • 14
    • 0142165072 scopus 로고    scopus 로고
    • β-helix: A lithography-based compliant off-chip interconnect
    • Zhu, Q. et al, "β-Helix: A Lithography-Based Compliant Off-Chip Interconnect," IEEE Trans on Components and Packaging Technologies, Vol. 26, No. 3 (2003), pp. 582-590.
    • (2003) IEEE Trans on Components and Packaging Technologies , vol.26 , Issue.3 , pp. 582-590
    • Zhu, Q.1
  • 15
    • 24644463337 scopus 로고    scopus 로고
    • Design, analysis, and development of novel three-dimensional stacking WLCSP
    • Yuan, C-A. et al., "Design, Analysis, and Development of Novel Three-Dimensional Stacking WLCSP," IEEE Trans on Advanced Packaging, Vol. 28, No. 3 (2005), pp. 387-396.
    • (2005) IEEE Trans on Advanced Packaging , vol.28 , Issue.3 , pp. 387-396
    • Yuan, C.-A.1
  • 18
    • 0036610810 scopus 로고    scopus 로고
    • Densely packed optoelectronic interconnect using micromachined springs
    • Chua, C. L. et al, "Densely Packed Optoelectronic Interconnect using Micromachined Springs," IEEE Photonics Technology Letters, Vol. 14, No. 6 (2002), pp. 846-848.
    • (2002) IEEE Photonics Technology Letters , vol.14 , Issue.6 , pp. 846-848
    • Chua, C.L.1
  • 19
    • 0037674307 scopus 로고    scopus 로고
    • Intermittency study of a stressed-metal micro-spring sliding electrical contact
    • New Orleans, LA, May.
    • rd Electronic Components and Technology Conf, New Orleans, LA, May. 2003, pp. 1714-1717.
    • (2003) rd Electronic Components and Technology Conf , pp. 1714-1717
    • Chow, E.M.1
  • 22
    • 31044437398 scopus 로고    scopus 로고
    • Process integration for through-silicon vias
    • S. Spiesshoefer, S. et al., "Process Integration for Through-Silicon Vias," J. Vac. Sci. Technol. A, Vol. 23, No. 4 (2005), pp. 824-829.
    • (2005) J. Vac. Sci. Technol. A , vol.23 , Issue.4 , pp. 824-829
    • Spiesshoefer, S.S.1
  • 23
    • 31144461233 scopus 로고    scopus 로고
    • Control of sidewall slope in silicon vias using SF6/02 plasma etching in a conventional reactive ion etching tool
    • Figueroa, R. F. et al., "Control of Sidewall Slope in Silicon Vias Using SF6/02 Plasma Etching in a Conventional Reactive Ion Etching Tool," J. Vac. Sci. Technol. B, Vol. 23, No. 5 (2005), pp. 2226-2231.
    • (2005) J. Vac. Sci. Technol. B , vol.23 , Issue.5 , pp. 2226-2231
    • Figueroa, R.F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.