Real chip size three-dimensional stacked package

IEEE Transactions on Advanced Packaging

Volumn 28, Issue 3, 2005, Pages 397-403

  Yamazaki, Takao ^a   Sogawa, Yoshimichi ^a   Yoshino, Rieka ^b   Kata, Keiichiro ^b   Hazeyama, Ichiro ^a   Kitajo, Sakae ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Flexible printed circuit (FPC); Flip chip; Gold stud bump; Solder bump; Stacked multichip package; Thermoplastic resin; Three dimensional stacked package

Indexed keywords

CHIP SCALE PACKAGES; FLIP CHIP DEVICES; MULTICHIP MODULES; PRINTED CIRCUITS; THERMOPLASTICS;

FLEXIBLE PRINTED CIRCUITS; GOLD STUD BUMP; SOLDER BUMP; STACKED MULTICHIP PACKAGE; THREE DIMENSIONAL STACKED PACKAGE;

ELECTRONICS PACKAGING;

EID: 24644447011     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2005.852328     Document Type: Article

References (10)

1. Y. Fukui, Y. Yano, H. Juso, Y. Matsune, K. Miyata, A. Narai, Y. Sota, Y. Takeda, K. Fujita, and M. Kada, "Triple-chip stacked CSP," in Proc. Electronic Components Technology Conf., 2000, pp. 385-389.
2. T. Imoto, M. Matsui, C. Takubo, S. Akejima, T. Kariya, T. Nishikawa, and R. Enomoto, "Development of 3-dimensional module package; System block module," in Proc. Electronic Components Technology Conf., 2001, pp. 552-557.
3. N. Takahashi, N. Senba, Y. Shimada, I. Morizaki, and K. Tokuno, "3-dimensional memory module," in Proc. Electronic Components Technology Conf., 1996, pp. 113-118.
4. K. Takahashi, M. Hoshino, H. Yonemura, M. Tomisaka, M. Sunohara, M. Tanioka, T. Sato, K. Kojima, and H. Terao, "Development of advanced 3-D chip stacking technology with ultra-fine interconnection," in Proc. Electronic Components Technology Conf., 2001, pp. 541-546.
5. "Two types of stacked CSP, flip-chip type of chip stacking CSP and package-on-package type of CSP, will be starting mass production" (in Japanese), NIKKEI MICRODEVICES, p. 144, Jul. 1999.
6. "Ultrathin package that can systemize by multichip stacking is developed" (in Japanese), NIKKEI MICRODEVICES, p. 158, Mar. 2000.
7. C. Mitchell, "Identifying and addressing the challenges of logic and memory integration," J. Jpn. Inst. Electron. Packag., vol. 7, no. 5, pp. 401-404, Aug. 2004.
8. J. Vardaman, "Stacked CSPs: Market and technology developments," in Proc. 10th Annu. Int. KGD Packaging Test Workshop, Sep. 8-10, 2003.
9. C. E. Bauer and J. Riley, "Multichip packaging: Business and logistical issues," Adv. Packag., p. 29, Jan. 2003.
10. L. Smith, "Applications and advances in chip scale packaging stacking," in Proc. IMAPS Advanced Technology Workshop Advanced 3-D Packaging, Mar. 12, 2003.