Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

IEEE Transactions on Electron Devices

Volumn 50, Issue 10, 2003, Pages 2039-2048

  Bakir, Muhannad S ^a   Reed, Hollie A ^a   Thacker, Hiren D ^a   Patel, Chirag S ^a,b   Kohl, Paul A ^a   Martin, Kevin P ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Air gaps; Interconnections; Microelectromechanical devices; Packaging

Indexed keywords

DENSITY (SPECIFIC GRAVITY); ELECTRIC PROPERTIES; INDENTATION; INPUT OUTPUT PROGRAMS; INTEGRATED CIRCUIT TESTING; MECHANICAL PROPERTIES; PRINTED CIRCUIT BOARDS; SILICON WAFERS; THERMAL CYCLING; THERMAL EXPANSION;

GIGASCALE INTEGRATION; SEA OF LEADS; ULTRAHIGH DENSITY WAFER LEVEL CHIP INTERCONNECTIONS;

LEAD;

EID: 0141940290     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.816528     Document Type: Article

References (36)

1. J. Meindl, J. Davis, P. Zarkesh-Ha, C. Patel, K. Martin, and P. Kohl, "Interconnect opportunities for gigascale integration," IBM J. Res. Develop., vol. 46, pp. 245-262, Mar./May 2002.
2. J. Meindl, R. Venkatesan, J. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. Baker, A. Mule, P. Kohl, and K. Martin, "Interconnecting device opportunities for gigascale integration (GSI)," in IEDM Tech. Dig., 2001, pp. 525-528.
3. J. D. Meindl, "Low power microelectronics: retrospect and prospect," Proc. IEEE, vol. 83, pp. 619-635, Apr. 1995.
4. International Technology Roadmap for Semiconductors (ITRS): SIA, 2002.
5. R. Tummala, Fundamentals of Microsystems Packaging. New York: McGraw-Hill, 2001.
6. W. Brown, Advanced Electronic Packaging. New York: IEEE Press, 1999.
7. Z. Feng, W. Zhang, B. Su, K. C. Gupta, and Y. C. Lee, "RF and mechanical characterization of flip-chip interconnects in CPW circuits with underfill," IEEE Trans. Microwave Theory Tech., vol. 46, pp. 2269-2275, Dec. 1998.
8. H. Kusamitsu, Y. Morishita, K. Maruhashi, M. Ito, and K. Ohata, "The flip-chip bump interconnection for millimeter-wave GaAs MMIC," in Proc. Int. Conf. on Multichip Modules and High Density Packaging, 1998, pp. 47-52.
9. Y.-G. Kim, I. Mohammed, B.-S. Seol, and T.-G. Kang, "Wide area vertical expansion (WAVE) package design for high speed application: reliability and performance," in Proc. Electronics Components and Technology Conf., 2001, pp. 54-62.
10. J. Novitsky and C. Miller, "MicroSpring contacts on silicon: delivering Moore's law-type scaling to semiconductor package, test and assembly," in Proc. Int. Conf. and Exhibition on High-Density Interconnect and Systems Packaging, 2000, pp. 250-255.
11. R. Fillion, R. Wojnarowski, H. Colc, and G. Claydon, "On-wafer process for stress-free area array floating pads," in Proc. Int. Symp. Microelectronics, 2001, pp. 100-105.
12. L. Ma, Q. Zhu, T. Hantschel, D. Fork, and S. Sitaraman, "J-springs - innovative compliant interconnects for next-generation packaging," in Proc. Electronic Components and Technology Conf., 2002, pp. 1359-1365.
13. D. Smith, D. Fork, R. Thornton, A. Alimonda, C. Chua, C. Dunnrowicz, and J. Ho, "Flip-chip bonding on 6-μm pitch using thin-film microspring technology," in Proc. Electronic Components and Technology Conf., 1998, pp. 325-329.
14. Q. Zhu, L. Ma, and S. Sitaraman, "Design and optimization of a novel compliant off-chip interconnect one-turn helix," in Proc. Electronic Components and Technology Conf., 2002, pp. 910-914.
15. R. Marcus, "A new coiled microspring contact technology," in Proc. Electronic Components and Technology Conf., 2001, pp. 1227-1232.
16. Y. H. Joung and M. G. Allen, "Micromachined flexible interconnect for wafer level packaging," in Proc. ASME Int. Mechanical Eng. Congr. Expo., 2001.
17. M. Rasco, K. Mosig, L. Jamin, P. Elenius, and R. Augur, "Packaging assessment of porous ultra low-k materials," in Proc. Int. Interconnect Technology Conf., 2002, pp. 113-115.
18. M. Bakir, H. Reed, P. Kohl, K. Martin, and J. Meindl, "Sea of Leads ultra-high density compliant wafer level packaging technology," in Proc. Electronic Components and Technology Conf., 2002, pp. 1087-1094.
19. M. Bakir, H. Reed, A. Mule, J. Jayachandran, P. Kohl, K. Martin, T. Gaylord, and J. Meindl, "Chip-to-module interconnections using 'Sea of Leads' technology," MRS Bull., vol. 28, no. 1, pp. 61-67, 2001.
20. M. Bakir, A. Mule, H. Thacker, P. Kohl, K. Martin, and J. Meindl, "SoL compliant wafer-level package technologies," Semicond. Int. Mag., pp. 61-64, April 2002.
21. C. S. Patel, "Compliant Wafer-Level Package (CWLP)," Ph.D. dissertation, Georgia Inst. Technol., Atlanta, 2001.
22. C. Patel, C. Power, M. Realff, P. Kohl, K. Martin, and J. Meindl, "Low cost high density compliant wafer level package," in Proc. Int. Conf. High-Density Interconnect and Systems Packaging, 2000, pp. 335-339.
23. C. Patel, K. Martin, and J. Meindl, "Electrical performance of compliant wafer-level package," in Proc. Electronic Components and Technology Conf., 2001, pp. 1380-1383.
24. H. Reed, C. White, V. rao, S. Bidstrup-Allen, C. Henderson, and P. Kohl, "Fabrication of microchannels using polycarbonates as sacrificial materials," J. Micromech. Microeng., vol. 11, pp. 733-737, 2001.
25. D. Bhusari, H. Reed, M. Wedlake, A. Padovani, S. Bidstrup-Allen, and P. Kohl, "Fabrication of air-channel structures for microfluidic, microelectromechanical, and microelectronic applications," J. Microelectromech. Syst., vol. 10, pp. 400-408, 2001.
26. X. Wu, H. Reed, L. Rhodes, E. Elce, R. Ravikiran, R. Shick, C. Henderson, S. Allen, and P. Kohl, "Lithographic characteristics and thermal processing of photosensitive sacrificial materials," J. Electrochemical Society, vol. 149, pp. 555-561, 2002.
27. D. Conti and J. Horn, "Wafer level burn-in," in Proc. Dlectronic Components and Technology Conf., 2000, pp. 815-821.
28. M. Bakir, H. Thacker, Z. Zhou, P. Kohl, K. Martin, and J. Meindl, "Sea of lead microwave characterization and process integration with FEOL & BEOL," in Proc. Int. Interconnect Technology Conf., 2002, pp. 116-118.
29. P. Zarkesh-Ha and J. Meindl, "An integrated architecture for global interconnects in a gigascale system-on-a-chip (GSoC)," in Proc. Symp. VLSI Technology, 2000, pp. 194-195.
30. ____, "Optimum on-chip power distribution networks for gigascale integration (GSI)," in Proc. Int. Interconnect Technology Conf., 2001, pp. 125-127.
31. J. Meindl, "The evolution of monolithic and polylithic interconnect technology," in Proc. IEEE VLSI Circuits Symp., 2002, pp. 2-5.
32. A. Naeemi, C. Patel, M. Bakir, P. Zarkesh-Ha, K. Martin, and J. Meindl, "Sea of Leads: a disruptive paradigm for a system-on-a-chip," in Proc. Int. Solid-State Circuits Conf., 2001, pp. 280-281.
33. S. Afonso , L. Schaper, J. Parkerson, W. Brown, S. Ang, and H. Naseem, "Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects," IEEE Trans. Adv. Packag., vol. 22, pp. 309-320, Aug. 1999.
34. L. Arledge and W. Lynch, "Scaling and performance implications for power supply an other signal routing constraints imposed by I/O pad limitations," in Proc. IEEE Symp. IC/Package Design Integration, 1998, pp. 45-50.
35. S. Mourad and Y. Zorian, Principles of Testing Electronic Systems, New York: Wiley, 2000.
36. H. Thacker, M. Bakir, D. Keezer, K. Martin, and J. Meindl, "Compliant probe substrates for testing high pin-count chip scale packages," in Proc. Electronics and Component Technology Conf., 2002, pp. 118-1193.