Smart Three Axis Compliant (STAC) interconnect: An ultra-high density MEMS based interconnect for wafer-level ultra-thin die stacking technology

Proceedings - Electronic Components and Technology Conference

Volumn 2, Issue , 2005, Pages 1089-1093

  Arunasalam, Parthiban ^a   Ackler, Harold D ^a   Sammakia, Bahgat G ^a  

^a BINGHAMTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PACKAGE COEFFICIENT; SMART THREE AXIS COMPLAINT (STAC) INTERCONNECT; STAG INTERCONNECTS; ULTRA-THIN CHIPS;

DIES; ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; OPTICAL INTERCONNECTS; SILICON; SILICON WAFERS; THERMAL EXPANSION;

MICROELECTROMECHANICAL DEVICES;

EID: 24644476549     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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