Metrology challenges for 45-nm strained-Si device technology

IEEE Transactions on Semiconductor Manufacturing

Volumn 19, Issue 4, 2006, Pages 381-388

  Vartanian, Victor ^a,b   Zollner, Stefan ^b   Thean, A V Y ^b   White, T ^b   Nguyen, B Y ^b   Prabhu, L ^b   Eades, D ^b   Parsons, S ^b   Desjardins, H ^b   Kim, K ^b   Jiang, Z X ^b   Dhandapani, V ^b   Hildreth, J ^b   Powers, R ^b   Spencer, G ^b   Ramani, N ^b   Kottke, M ^b   Canonico, M ^b   Wang, X D ^b   Contreras, L ^b   Theodore, D ^b   Gregory, R ^b   Venkatesan, S ^b   more..

^a IEEE   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

CMOS integrated circuits; Metrology; Strain measurement

Indexed keywords

BULK SUBSTRATES; CARRIER LIFETIMES; NONDESTRUCTIVE INLINE METROLOGY; POWER SUPPLY VOLTAGES;

CARRIER MOBILITY; ELECTRONICS INDUSTRY; MOSFET DEVICES; PHOTOLUMINESCENCE; POWER SUPPLY CIRCUITS; RAMAN SPECTROSCOPY; SILICON ON INSULATOR TECHNOLOGY; STRAIN MEASUREMENT; SURFACE ROUGHNESS;

CMOS INTEGRATED CIRCUITS;

EID: 33751525115     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2006.884603     Document Type: Conference Paper

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