Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 953-958

  Bhardwaj, Sarvesh ^a   Caot, Yu ^a   Vrudhula, Sarma ^a  

^a Arizona State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; DIGITAL CIRCUITS; LEAKAGE CURRENTS; OPTIMIZATION; STATISTICAL METHODS; THRESHOLD VOLTAGE;

DELAY MODELS; DESIGN VARIABLES; STATISTICAL LEAKAGE MINIMIZATION; STATISTICAL OPTIMIZATION;

GATES (TRANSISTOR);

EID: 33748595524     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118513     Document Type: Conference Paper

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