Circuit design techniques for a first-generation cell broadband engine processor

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 8, 2006, Pages 1692-1704

  Warnock, James ^a,b   Wendel, Dieter ^c   Aipperspach, Tony ^b   Behnen, Erwin ^b   Cordes, Robert A ^b   Dhong, Sang H ^b   Hirairi, Koji ^d   Murakami, Hiroaki ^e,f   Onishi, Shohji ^g   Pham, Dac C ^b   Pille, Jürgen ^c   Posluszny, Stephen D ^b   Takahashi, Osamu ^b   Wen, Huajun ^b  

^a IEEE   (United States)

^b IBM   (United States)

^c IBM   (Germany)

^d Sony Computer Entertainment Inc   (United States)

^e Toshiba America Inc   (United States)

^f TOSHIBA CORPORATION   (Japan)

^g IBM JAPAN LTD   (Japan)

Author keywords

90 nm SOI; Cell broadband engine; Cell circuits; Cell processor; Delayed reset domino; Flip flop design; Media centric computing; Modularity; Multi core; Semi custom circuit design; SoC; Synergistic processor

Indexed keywords

90-NM SOI; CELL BROADBAND ENGINE; CELL CIRCUITS; CELL PROCESSOR; DELAYED RESET DOMINO; MEDIA-CENTRIC COMPUTING; MODULARITY; SEMI-CUSTOM CIRCUIT DESIGN; SOC; SYNERGISTIC PROCESSOR;

FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS;

LOGIC CIRCUITS;

EID: 33746912373     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.877234     Document Type: Conference Paper

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