Clocking and circuit design for a parallel I/O on a first-generation CELL processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Chang, Ken ^a   Pamarti, Sudhakar ^a   Kaviani, Kambiz ^a   Alon, Elad ^a,b   Shi, Xudong ^a   Chin, T J ^a   Shen, Jie ^a   Yip, Gary ^a   Madden, Chris ^a   Schmitt, Ralf ^a   Yuan, Chuck ^a   Assaderaghi, Fari ^a   Horowitz, Mark ^a,b  

^a Rambus   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 25844490996     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D. Pham et al., The Design and Implementation of a First-Generation Cell Processor," ISSCC Dig. Tech. Papers, Paper 10.2, pp. 182-183, Feb., 2005.
2. K. Chang et al., "A 0.4-4Gb/s CMOS Quad Transceiver Cell using On-chip Regulated Dual-Loop PLLs," IEEE J. Solid-State Circuits, vol. 38, pp. 747-754, May., 2003.
3. E. Yeung et al., "A 2.4Gb/s/pin Simultaneous Bidirectional Parallel Link with Per Pin Skew Compensation," IEEE J. Solid-State Circuits, vol. 35. pp. 1619-1628, Nov., 2000.
4. P. Landman et al., "A 62Gb/s Backplane Interconnect ASIC Based on 3.1Gb/s Serial-Link Technology," ISSCC Dig. Tech. Papers, pp. 72-73, Feb., 2002.