Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor

IBM Journal of Research and Development

Volumn 41, Issue 4-5, 1997, Pages 489-501

  Sigal, L ^a   Warnock, J D ^a   Curran, B W ^a   Chan, Y H ^a   Camporese, P J ^a   Mayo, M D ^a   Huott, W V ^a   Knebel, D R ^a   Chuang, C T ^a   Eckhardt, J P ^a   Wu, P T ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PHASE LOCKED LOOPS; TIMING CIRCUITS;

SELF RESETTING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUITS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0031175456     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.414.0489     Document Type: Article

References (7)

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