A streaming processing unit for a CELL processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages 134-135

  Flachs, B ^a   Asano, S ^c   Dhong, S H ^a   Hofstee, P ^a   Gervais, G ^a   Kim, R ^a   Le, T ^a   Liu, P ^a   Leenstra, J ^b   Liberty, J ^a   Michael, B ^a   Oh, H ^a   Mueller, S M ^b   Takahashi, O ^a   Hatakeyama, A ^d   Watanabe, Y ^c   Yano, N ^c  

^a IBM   (United States)

^b IBM   (Germany)

^c TOSHIBA CORPORATION   (Japan)

^d SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 27644524078     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. O. Takahashi et al., "The Circuits and Physical Design of the Streaming Processor of a CELL Processor," submitted to Symp. VLSI Circuits, June, 2005.
2. D. Pham et al., "The Design and Implementation of a First-Generation CELL Processor," ISSCC Dig. Tech. Papers, Paper 10.2, pp. 184-185, Feb., 2005.
3. T. Asano et al., "A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processing of a CELL Processor," ISSCC Dig. Tech. Papers, Paper 26.7, pp. 486-487, Feb., 2005.
4. J. Leenstra et al., "The Vector Fixed Point Unit of the Streaming Processor of a CELL Processor," submitted to Symp. VLSI Circuits, June, 2005.
5. H. Oh et al., "A Fully-Pipelined Single-Precision Floating Point Unit in the Streaming Processing Unit of a CELL Processor," submitted to Symp. VLSI Circuits, June, 2005.