The circuits and physical design of the synergistic processor element of a CELL processor

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 20-23

  Takahashi, O ^a   Cook, R ^a   Cottier, S ^a   Dhong, S H ^a   Flachs, B ^a   Hirairi, K ^e   Kawasumi, A ^f   Murakami, H ^f   Noro, H ^f   Oh, H ^a   Onishi, S ^b   Pille, J ^c   Silberman, J ^d   Yong, S ^a  

^a IBM   (United States)

^b IBM JAPAN LTD   (Japan)

^c IBM   (Germany)

^d IBM T J WATSON RESEARCH CENTER   (United States)

^e Sony Computer Entertainment Inc   (United States)

^f Toshiba America Inc   (United States)

Author keywords

CMOS; Multi Core Processor; SOI; Streaming; VLSI

Indexed keywords

CELL PROCESSOR; MICROARCHITECTURE; MULTI CORE PROCESSORS; STREAMING;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; SILICON ON INSULATOR TECHNOLOGY;

VLSI CIRCUITS;

EID: 28244471705     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469324     Document Type: Conference Paper

References (7)

1. B. Flachs et al., "A Streaming Processor Unit of a CELL Processor," appears in ISSCC 2005
2. D. Pham et al., "The Design and Implementation of a First-Generation CELL Processor," appears in ISSCC 2005
3. E. Behnen et al., "Ontology of a First-generation CELL Processor," submitted to 2005 Design Automation Conference
4. T. Asano et al., "A 4.8GHz fully pipelined embedded SRAM in the Streaming Processor of a CELL Processor," appears in ISSCC 2005
5. J. Leenstra et al., "The Vector Fixed Point Unit of the Synergistic Processor Element of a CELL Processor," submitted to 2005 VLSI Circuit Symposium
6. H. Oh et al., "A Fully-Pipelined Single-Precision Floating Point Unit in the Synergistic Processor Element of a CELL Processor," submitted to 2005 VLSI Circuits Symposium
7. R. Chaudhry et al., "A Cycle Accurate Power Estimation Tool," submitted to 2005 Design Automation Conference