A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Kuang, J B ^a   Buchholtz, T C ^a   Dance, S M ^a   Warnock, J D ^a   Storino, S N ^a   Wendel, D ^b   Bradley, D H ^a  

^a IBM   (United States)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 25844514370     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. D. Pham et al., "The Design and Implementation of a First-Generation CELL Processor," ISSCC Dig. Tech. Papers, Paper 10.2, pp. 184-185, Feb., 2005.
2. S. Vangal et al., "A 5GHz Floating Point Multiply-Accumulator in 90nm Dual Vt CMOS," ISSCC Dig. Tech. Papers, pp. 336-337, Feb., 2003.
3. W. Belluomini et al., "An 8GHz Floating-Point Multiply," ISSCC Dig. Tech. Papers, Paper 20.1, pp. 374-375, Feb., 2005.