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Volumn 2005, Issue , 2005, Pages 45-49

The design methodology and implementation of a first-generation CELL processor: A multi-core SoC

Author keywords

64 bit Power Architecture; CELL processor; Flexible IO; Hardware content protection; Linux; Modularity; Multi core; Multi operating system; Multi threading; Re use; Real time system; SoC; SOI; Synergistic processor; Virtualization technology

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; INTERFACES (COMPUTER); PROGRAM PROCESSORS; REAL TIME SYSTEMS; SILICON ON INSULATOR TECHNOLOGY;

EID: 33847098374     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568604     Document Type: Conference Paper
Times cited : (14)

References (4)
  • 1
    • 33847152036 scopus 로고    scopus 로고
    • D. Pham et al, The Design and Implementation of a First-Generation CELL Processor, ISSCC'05 Paper #10.2
    • D. Pham et al, "The Design and Implementation of a First-Generation CELL Processor", ISSCC'05 Paper #10.2
  • 2
    • 33847157786 scopus 로고    scopus 로고
    • B. Flachs et al, The Microarchitecture of the Streaming Processor for a CELL Processor, ISSCC'05 Paper #7.4
    • B. Flachs et al, "The Microarchitecture of the Streaming Processor for a CELL Processor", ISSCC'05 Paper #7.4
  • 3
    • 33847147937 scopus 로고    scopus 로고
    • T. Asano et al, A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor, ISSCC'05 Paper #26.7
    • T. Asano et al, "A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor", ISSCC'05 Paper #26.7
  • 4
    • 33847162676 scopus 로고    scopus 로고
    • K. Chang et al, Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor, ISSCC'05 Paper #28.9
    • K. Chang et al, "Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor", ISSCC'05 Paper #28.9


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.