A fully-pipelined single-precision floating point unit in the synergistic processor element of a CELL processor

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 24-27

  Oh, Hwa Joon ^a   Mueller, Silvia M ^b   Jacobi, Christian ^b   Tran, Kevin D ^a   Cottier, Scott R ^a   Michael, Brad W ^a   Nishikawa, Hiroo ^c   Totsuka, Yonetaro ^d   Namatame, Tatsuya ^e   Yano, Naoka ^e   Machida, Takashi ^e   Dhong, Sang H ^a  

^a IBM   (United States)

^b IBM   (Germany)

^c IBM JAPAN LTD   (Japan)

^d Sony Computer Entertainment Inc   (United States)

^e Toshiba America Inc   (United States)

Author keywords

CMOS; Floating point unit; Microprocessor; SOI; Static circuits; VLSI

Indexed keywords

CELL PROCESSOR; DATA STREAMING; FLOATING POINT UNIT; STATIC CIRCUITS;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; SILICON ON INSULATOR TECHNOLOGY; VLSI CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 28244473720     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. B. Flachs et. al., "The microarchitecture of the streaming processor for a CELL processor," accepted for 2005 IEEE International Solid-State Circuits Conference (ISSCC-2005).
2. O. Takahashi et. al., "The circuits and physical design of the synergistic processor element of a CELL processor", submitted to 2005 VLSI Circuits Symposium (VLSI-2005).
3. N. Rohrer et. al., "PowerPC 970 in 130nm and 90nm technologies," ISSCC Dig. Tech. Papers, pp.68-69, Feb. 2004.
4. S. M. Mueller et. al., "The vector floating-point unit in a synergistic processor element of a CELL processor," submitted to 2005 IEEE 17th Symposium on Computer Arithmetic (ARITH-17).
5. D. Pham et. al., "The design and implementation of a first-generation CELL processor," accepted for 2005 IEEE International Solid-State Circuits Conference (ISSCC-2005).
6. V. G. Oklobdzija et. al., "A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach," IEEE Transactions on Computers, Vol. 45, No.3, pp. 294-305, March 1996