Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 5, 2006, Pages 514-524

  Dhillon, Yuvraj S ^a,b,c   Diril, Abdulkadir U ^a,b,d   Chatterjee, Abhijit ^a,e   Singh, Adit D ^a,f  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c INTEL CORPORATION   (United States)

^d NVIDIA   (United States)

^e GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^f AUBURN UNIVERSITY   (United States)

Author keywords

Circuit analysis; Circuit optimization; Combinational logic circuits; Soft error tolerance

Indexed keywords

CIRCUIT OPTIMIZATION; COMBINATIONAL LOGIC CIRCUITS; NANOMETER CIRCUITS; SOFT ERROR TOLERANCE;

COMBINATORIAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; ESTIMATION; FAULT TOLERANT COMPUTER SYSTEMS; OPTIMIZATION; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 33746464080     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.876104     Document Type: Article

References (18)

1. V. De and S. Borkar, "Technology and design challenges for low power and high performance," in Proc. ISLPED, 1999, pp. 163-168.
2. P. E. Dodd and L. W. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," IEEE Trans. Nucl. Sci., vol. 50, pp. 583-602, 2003.
3. P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, "Modeling the effect of technology trends on the soft error rate of combinational logic," in Proc. ICDSN, 2002, pp. 389-98.
4. M. Nicolaidis and Y. Zorian, "On-line testing for VLSI - A compendium of approaches," JETTA, vol. 12, pp. 583-602, 1998.
5. M. Nicolaidis, "Time redundancy based soft-error tolerance to rescue nanometer technologies," in Proc. VTS, 1999, pp. 86-94.
6. K. Mohanram and N. A. Touba, "Cost-effective approach for reducing soft error failure rate in logic circuits," in Proc. ITC, 2003, pp. 893-901.
7. M. Oman, G. Papasso, D. Rossi, and C. Metra, "A model for transient fault propagation in combinatorial logic," in Proc. IOLTS, 2003, pp. 111-15.
8. Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation," in Proc. CICC, 2000, pp. 201-204.
9. C. Zhao, X. Bai, and S. Dey, "A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits," in Proc. DAC, 2004, pp. 894-899.
10. L. B. Freeman, "Critical charge calculations for a bipolar SRAM array," IBM J. Res. Develop., vol. 40, pp. 119-129, 1996.
11. P. Hazucha, C. Svensson, and S.A. Wender, "Cosmic-ray soft error rate characterization of a standard 0.6-μm CMOS process," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1422-1429, Oct. 2000.
12. F. N. Najm and I. N. Hajj, "The complexity of fault detection in MOS VLSI circuits," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 9, pp. 995-1001, 1990.
13. M. Zhang and N.R. Shanbhag, "A soft-error rate analysis (SERA) methodology," in Proc. ICCAD, 2004, pp. 111-118.
14. Y. S. Dhillon, A. U. Diril, A. Chatterjee, and H. H. S. Lee, "Algorithm for achieving minimum energy consumption in CMOS circuits using multiple supply and threshold voltages at the module level," in Proc. ICCAD, 2003, pp. 693-700.
15. Y. S. Dhillon, A. U. Diril, and A. Chatterjee, "Soft-error tolerance analysis and optimization of nanometer circuits," in Proc. DATE, 2005, pp. 288-293.
16. W. Huyer and A. Neumaier, "Global optimization by multilevel coordinate search," J. Global Optimiz., vol. 14, no. 4, pp. 331-355, 1999.
17. S. C. Wong, G. Y. Lee, and D. J. Ma, "Modeling of interconnect capacitance, delay and crosstalk in VLSI," IEEE Trans. Semicond. Manuf., vol. 13, no. 1, pp. 108-111, 2000.
18. A. U. Diril, Y. S. Dhillon, A. Chatterjee, and A. D. Singh, "Design of adaptive nanometer digital systems for effective control of soft error tolerance," in Proc. VTS, 2005, pp. 298-303.