Accumulation gate capacitance of MOS devices with ultrathin high-κ gate dielectrics: Modeling and characterization

IEEE Transactions on Electron Devices

Volumn 53, Issue 6, 2006, Pages 1364-1372

  Islam, Ahmad Ehteshamul ^a,b   Haque, Anisul ^a,c  

^a BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY   (Bangladesh)

^b Purdue University   (United States)

^c EAST WEST UNIVERSITY   (Bangladesh)

Author keywords

High dielectric; MOS capacitors; Parameter extraction; Quantum mechanical (QM) modeling

Indexed keywords

APPROXIMATION THEORY; CAPACITANCE; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC DEVICES; GATES (TRANSISTOR); SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES;

PARAMETER EXTRACTION; QUANTUM-MECHANICAL MODELING; SEMICONDUCTOR CAPACITANCE;

MOS DEVICES;

EID: 33744783430     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.873845     Document Type: Article

References (27)

1. The International Technology Roadmap for Semiconductors. (2004). [Online]. Available: http://www.itrs.net/Common/2004Update/2004Update.htm
2. G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-k gate dielectrics: Current status and materials properties considerations," J. Appl. Phys., vol. 89, no. 10, pp. 5243-5275, May 2001.
3. A. Haque, A. Rahman, and I. B. Chowdhury, "On the use of appropriate boundary conditions to calculate the normalized wave functions in the inversion layer of MOSFETs with ultrathin gate oxides," Solid State Electron., vol. 44, no. 10, pp. 1833-1836, Oct. 2000.
4. S. Mudanai, Y.-Y. Fan, Q. Ouyang, A. F. Tasch, and S. K. Banerjee, "Modeling of direct tunneling current through gate dielectric stacks," IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1851-1857, Oct. 2000.
5. S. Mudanai, L. F. Register, A. F. Tasch, and S. K. Banerjee, "Understanding the effects of wave function penetration on the inversion layer capacitance of NMOSFETs," IEEE Electron Device Lett., vol. 22, no. 3, pp. 145-147, Mar. 2001.
6. A. Haque and M. Z. Kauser, "A comparison of wave-function penetration effects on gate capacitance in deep submicron n- and p-MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1580-1587, Sep. 2002.
7. J. Suñé, P Olivo, and B. Ricco, "Self-consistent solution of Poisson and Schrödinger equations in accumulation semiconductor-insulator interfaces," J. Appl. Phys., vol. 70, no. 1, pp. 337-345, Jul. 1991.
8. W. K. Chim, J. X. Zheng, and B. H. Koh, "Modeling of charge quantization and wave function penetration effects in a metal-oxide-semiconductor system with ultrathin gate oxide," J. Appl. Phys., vol. 94, no. 8, pp. 5273-5277, Oct. 2003.
9. M. M. A. Hakim and A. Haque, "Accurate modeling of gate capacitance in deep submicron MOSFETs with high-k gate-dielectrics," Solid State Electron., vol. 48, no. 7, pp. 1095-1100, Jul. 2004.
10. F. Rana, S. Tiwari, and D. A. Buchanan, "Self-consistent modeling of accumulation layers and tunneling currents through very thin oxides," Appl. Phys. Lett., vol. 69, no. 8, pp. 1104-1106, Aug. 1996.
11. S. Kar, "Extraction of the capacitance of ultrathin high-k gate dielectrics," IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2112-2119, Oct. 2003.
12. S. Kar, S. Rawat, S. Rakheja, and D. Reddy, "Characterization of accumulation layer capacitance for extracting data on high-k gate dielectrics," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1187-1193, Jun. 2005.
13. M. J. McNutt and C. T. Sah, "Determination of the MOS oxide capacitance," J. Appl. Phys., vol. 46, no. 9, pp. 3909-3913, Sep. 1975.
14. J. Maserjian, G. Petersson, and C. Svensson, "Saturation capacitance of thin oxide MOS structures and the effective surface density of states of silicon," Solid State Electron., vol. 17, no. 4, pp. 335-339, Apr. 1974.
15. C.-Y. Hu, D. L. Kencke, S. Banerjee, B. Bandyopadhyay, E. Ibok, and S. Garg, "Determining effective dielectric thicknesses of metal-oxide-semiconductor structures in accumulation mode," Appl. Phys. Lett., vol. 66, no. 13, pp. 1638-1640, Mar. 1995.
16. K. Ahmed, E. Ibok, G. Bains, D. Chi, B. Ogle, J. J. Wortman, and J. R. Hauser, "Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime," IEEE Trans. Electron Devices, vol. 47, no. 7, pp. 1349-1354, Jul. 2000.
17. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, ch. 1.
18. Quantum-Mechanical CV Simulator of Univ. California, Berkeley Device Group. [Online]. Available: Www-device.eecs.berkeley.edu/qmcv/index.shtml
19. J. J. Chambers and G. N. Parsons, "Physical and electrical characterization of ultrathin yttrium silicate insulators on silicon," J. Appl. Phys., vol. 90, no. 2, pp. 918-933, Jul. 2001.
20. 2 gate dielectrics,"Appl. Phys. Lett., vol. 81, no. 9, pp. 1663-1665, Aug. 2002.
21. K. Yang and C. Hu, "MOS capacitance measurement for high-leakage thin dielectrics," IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1500-1501, Jul. 1999.
22. D. W. Barlage, J. T. O'Keeffe, J. T. Kavalieros, M. M. Nguyen, and R. S. Chau, "Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit," IEEE Electron Device Lett., vol. 21, no. 9, pp. 454-456, Sep. 2000.
23. O. Simonetti, T. Maurel, and M. Jourdain, "Characterization of ultrathin metal-oxide-semiconductor structures using coupled current and capacitance-voltage models based on quantum calculations," J. Appl. Phys., vol. 92, no. 8, pp. 4449-4458, Oct. 2002.
24. G. D. Wilk, R. M. Wallace, and J. M. Anthony, "Hafnium and Zirconium silicates for advanced gate dielectrics," J. Appl. Phys., vol. 87, no. 1, pp. 484-492, Jan. 2000.
25. F. Li, S. Mudanai, L. F. Register, and S. K. Banerjee, "A physically based compact gate C-V model for ultrathin (EOT ∼ 1 nm and below) gate dielectric MOS devices," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1148-1158, Jun. 2005.
26. P. Q. Xuan and J. Bokor, "Investigation of NiSi and TiSi as CMOS gate materials," IEEE Electron Device Lett., vol. 24, no. 10, pp. 634-636, Oct. 2003.
27. 2 gate dielectric," in IEDM Tech. Dig., 2002, pp. 433-436.