A physically based compact gate C-V model for ultrathin (EOT ∼ 1 nm and below) gate dielectric MOS devices

IEEE Transactions on Electron Devices

Volumn 52, Issue 6, 2005, Pages 1148-1158

  Li, Fei ^a   Mudanai, Sivakumar ^b   Register, Leonard Franklin ^c   Banerjee, Sanjay K ^c  

^a Nassda Corporation   (United States)

^b INTEL CORPORATION   (United States)

^c The University of Texas at Austin   (United States)

Author keywords

Compact gate capacitance voltage (C V) modeling; Fermi Dirac statistics; Interface states; Quantum mechanical (QM) effects; Wave function penetration

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; FERMI LEVEL; GATES (TRANSISTOR); MATHEMATICAL MODELS; SEMICONDUCTING SILICON; SEMICONDUCTOR QUANTUM WELLS;

COMPACT GATE CAPACITANCE-VOLTAGE (C-V) MODELING; FERMI-DIRAC STATISTICS; INTERFACE STATES; QUANTUM-MECHANICAL (QM) EFFECTS; WAVE FUNCTION PENETRATION;

MOS DEVICES;

EID: 21044444453     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.848079     Document Type: Article

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