An improved electron and hole mobility model for general purpose device simulation

IEEE Transactions on Electron Devices

Volumn 44, Issue 9, 1997, Pages 1529-1538

  Darwish, Mohamed N ^a,b,c   Lentz, Janet L ^a,b   Pinto, Mark R ^a,c   Zeitzoff, Peter M ^a   Krutsick, Thomas J ^a   Vuong, Hong Ha ^a  

^a Siliconix Inc   (United States)

^b LUCENT TECHNOLOGIES   (United States)

^c SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; COMPUTER SIMULATION; CRYSTAL IMPURITIES; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC FIELD EFFECTS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SUBSTRATES; SURFACE ROUGHNESS; THERMAL EFFECTS;

COULOMB SCREENING;

MOSFET DEVICES;

EID: 0031236754     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.622611     Document Type: Article

References (25)

1. A.J. Walker and P. H. Worlee, "A mobility model for MOSFET device simulation," in Proc. Europ. Solid-State Dev. Res. Conf. (ESSDERC), 1988, p. 265.
2. C.-L. Huang and G.S. Gildenblat, "Measurements and modeling of the n-channel MOSFET inversion layer mobility and device characteristics in the temperature range 60-300 K," IEEE Trans. Electron Devices, vol. 37, p. 1289, May 1990.
3. S. Selberherr, W. Hänsch, M. Seavey, and J. Slotboom, "The evolution of the MINIMOS mobility model," Solid-State Electron., vol. 33, no. 11, p. 1425, 1990.
4. H. Shin, G.M. Yeric, A. F. Tasch, and C. M. Maziar, "Physically-based models for effective mobility and local-field mobility of electrons in MOS inversion layers," Solid-State Electron., vol. 34, no. 6, p. 545, 1991.
5. C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, "A physically-basedmobility model for numerical simulation of nonplanar devices," lEEE Trans. Computer-Aided Design, vol. 7, pp. 1164-1171, Nov. 1988.
6. S.A. Mujtaba, R. W. Dutton, and D. L. Scharfetter, "Semi-empirical local NMOS mobility model for 2-D device simulation incorporating screened impurity scattering," in Proc. NUPAD V, June 1994.
7. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the university of inversion-layer mobility in Si MOSFET's - Part I: Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, pp. 2357-2362, Dec. 1994.
8. M. Shirahata, H. Kusano, N. Kotani, S. Kusanoki, and Y. Akasaka, "A mobility model including the screening effect in MOS inversion layer," IEEE Trans. Computer-Aided Design, vol. 11, pp. 1114-1119, Sept. 1992.
9. A.G. Sabnis and J. T. Clemens, "Characterization of the electron mobility in the Inverted 〈100〉 Si substrate," in IEEE IEDM Tech. Dig., 1979, pp. 18-21.
10. D.B. M. Klaassen, "A unified mobility model for device simulation - Part I: Model equations and concentration dependence," Solid-State Electron., vol. 35, no. 7, pp. 953-959, 1992.
11. S. Mori and T. Ando, "Intersubband scattering effect on the mobility of a Si (100) inversion layer at low temperature," Phys. Rev.B., vol. 19, p. 6433, 1979.
12. S.A. Schwarz and S. E. Russek, "Semi-empirical equations for electron velocity in silicon - Part II: MOS inversion layer," IEEE Trans. Electron Devices, vol. ED-30, pp. 1634-1639, Dec. 1983.
13. A. Hartstein, T.H. Ning and, A. B. Fowler, "Electron scattering in silicon inversion layers by oxide and surface roughness," Surf. Sci., vol. 58, p. 178, 1976.
14. Y. Matsumoto and Y. Uemura, "Scattering mechanism and low temperature mobility of MOS inversion layers," Jpn.J. Appl. Phys., supp. 2. pt. 2, p. 367, 1974.
15. W. Haänsch and M. Miura-Mattausch, "A new current relation for hot electron transport," INASECODE IV, J.J. H. Miller, Ed. Dublin, Ireland: Boole, 1985, pp. 311-314.
16. K.K. Thornber, "Relation of drift velocity to low-field mobility and high-field saturation velocity," J. Appl. Phys., vol. 51, pp. 2127-2136, 1980.
17. K. Singhal, C.C. McAndrew, S. R. Nassif, and V. Visvanathan, "The CENTER design optimization system," AT&T Tech. J., vol. 68, no. 3, p. 77, May/June 1989.
18. C.-E. Huang, J.V. Faricelli, and N. D. Arora, "A new technique for measuring MOSFET inversion layer mobility," IEEE Trans. Electron Devices, vol. 40, pp. 1134-1139, June 1993.
19. J.T. Watt and J. D. Plummer, in 1987 Symp. VLSI Technol. Dig. Tech. Papers, 1987, p. 81.
20. V.M. Agostinelli, Jr., unpublished.
21. M.R. Pinto, C. S. Rafferty, R. K. Smith, and J. Bude, "ULSI technology development by predictive simulation," in IEDM Tech. Dig., 1993, p. 701.
22. B.R. Penumalli, "A comprehensive two-dimensional process simulation program, BICEPS," IEEE Trans. Electron Devices, vol. ED-30, Sept. 1983.
23. M.R. Pinto, D. M. Boulin, C. S. Rafferty, R. K. Smith, W. M. Coughran, I. C. Kizilyalli, and M. J. Thoma, "Three-dimensional characterization of bipolar transistors on a submicron BiCMOS technology using integrated process and device simulation," in IEDM 1992, p. 923.
24. C.S. Rafferty, H.-H. Vuong, S. A. Eshraghi, M. D. Giles, M. R. Pinto, and S. J. Hillenius, "Anomalous short-channel threshold voltage due to transient enhanced diffusion," in IEDM 1993, p. 311.
25. H.H. Vuong, C. S. Rafferty, S. A. Eshraghi, J. L. Lentz, P. M. Zeitzoff, M. R. Pinto, and S. J. Hillenius, "Effects of oxide interface traps and transient enhanced diffusion on the process modeling of PMOS devices," IEEE Trans. Electron Devices, vol. 43, p. 1144, 1996.