A framework for energy and transient power reduction during behavioral synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 6, 2004, Pages 562-572

  Mohanty, Saraju P ^a   Ranganathan, Nagarajan ^a  

^a University of South Florida   (United States)

Author keywords

Average power; Dynamic frequency clocking; Low power datapath scheduling; Multiple supply voltages; Peak power; Peak power differential; Power fluctuation

Indexed keywords

ALGORITHMS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; DYNAMIC PROGRAMMING; ELECTRIC POTENTIAL; ENERGY MANAGEMENT; INTEGER PROGRAMMING; LINEAR PROGRAMMING; SCHEDULING;

AVERAGE POWER; DYNAMIC FREQUENCY CLOCKING; LOW-POWER DATAPATH SCHEDULING; MULTIPLE SUPPLY VOLTAGES; PEAK POWER; PEAK POWER DIFFERENTIAL; POWER FLUCTUATIONS;

STANDBY POWER SYSTEMS;

EID: 3042651071     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.827568     Document Type: Article

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