Scheduling techniques for variable voltage low power designs

ACM Transactions on Design Automation of Electronic Systems

Volumn 2, Issue 2, 1997, Pages 81-97

  Lin, Yann Rue ^a,c   Hwang, Cheng Tsung ^b   Wu, Allen C H ^a,c  

^a TSINGHUA UNIVERSITY   (China)

^b PROVIDENCE UNIVERSITY   (Taiwan)

^c NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

High level synthesis; Lower power design; Scheduling; Variable voltage

Indexed keywords

EID: 0001920829     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/253052.253054     Document Type: Article

References (13)

1. CHANDRAKASAN, A., POTKONJAK, A., RABAEY, M., AND BRODERSEN, R. W. 1992a. HYPER-LP: A system for power minimization using architectural transformation. In Proceedings of the ICCAD (Santa Clara, CA, Nov.) 300-303.
2. CHANDRAKASAN, A., SHENG, A., AND BRODERSEN, R. W. 1992b. Lower-power CMOS design. IEEE J. Solid-State Circuits, 472-484.
3. CHANG, J.-M. AND PEDRAM, M. 1995. Lower power register allocation and binding. In Proceedings of the 32nd DAC (San Francisco, CA, June), 29-35.
4. DEVADAS, S. AND MALIK, S. 1995. A survey of optimization techniques targeting low power VLSI circuits. In Proceedings of the 32nd DAC (San Francisco, CA, June), 242-247.
5. LINDO 1985. LINDO: Linear Iteractive and Discrete Optimizer for Linear, Integer, and Quadratic Programming Problems. LINDO Systems, Inc., Chicago, IL.
6. MARTIN, R. S. AND KNIGHT, J. P. 1995. Power-profiler: Optimizing ASICs power consumption at the behavioral level. In Proceedings of the 32nd DAC (San Francisco, CA, June), 42-47.
7. MONTEIRO, J., DEVADAS, S., ASHAR, P., AND MAUSKAR, A. 1996. Scheduling techniques to enable power management. In Proceedings of the 33nd DAC (Las Vegas, NV, June), 349-352.
8. NAJM, F. N. 1994. A survey of power estimation techniques in VLSI circuits. IEEE Trans. VLSI Syst. 2, 4 (Dec.), 446-455.
9. NAJM, F. N. 1995. Power estimation techniques for integrated circuits. In Proceedings of the ICCAD (San Jose, CA, Nov.), 492-499.
10. PEDRAM, M. 1996. Power minimization in IC design: Principles and applications. ACM Trans. Des. Autom. Electron. Syst. 1, 1 (Jan.), 3-56.
11. RAGHUNATHAN, A. AND JHA, N. K. 1994. Behavioral synthesis for low power. In Proceedings of the ICCD (Cambridge, MA, Oct.), 318-322.
12. RAGHUNATHAN, A. AND JHA, N. K. 1995. An iterative improvement algorithm for low power. In Proceedings of the ICCD (Austin, TX, Oct.), 597-602.
13. RAJE, S. AND SARRAFZADEH, M. 1995. Variable voltage scheduling. In Proceedings of the International Symposium on Low Power Designs (Monterey, CA, Aug.), 9-13.