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Volumn 2, Issue 3, 1997, Pages 227-248

Datapath scheduling with multiple supply voltages and level converters

Author keywords

Algorithms; Datapath scheduling; Design additional; DSP; High level synthesis; Level conversion; Low power design; Multiple voltage; Power optimization; Scheduling

Indexed keywords


EID: 33747003362     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/264995.264997     Document Type: Article
Times cited : (75)

References (17)
  • 6
    • 11544258791 scopus 로고
    • An ILP model for simultaneous scheduling and partitioning for low power system mapping
    • Univ. of Waterloo April
    • GEBOTYS, C. H. 1995. An ILP model for simultaneous scheduling and partitioning for low power system mapping. Technical Report, Univ. of Waterloo (April).
    • (1995) Technical Report
    • Gebotys, C.H.1
  • 9
    • 0029378968 scopus 로고
    • Profile-driven behavioral synthesis for low-power VLSI systems
    • Fall
    • KUMAR, N., KATKOORI, S., RADER, L., AND VEMURI, R. 1995. Profile-driven behavioral synthesis for low-power VLSI systems. IEEE Des. Test Computers 12, 3 (Fall), 70-84.
    • (1995) IEEE Des. Test Computers , vol.12 , Issue.3 , pp. 70-84
    • Kumar, N.1    Katkoori, S.2    Rader, L.3    Vemuri, R.4
  • 13
    • 0029181478 scopus 로고
    • Variable voltage scheduling
    • (Dana Point, California, April 23-26, 1995). ACM Press, New York, NY
    • RAJE, S. AND SARRAFZADEH, M. 1995. Variable voltage scheduling. In Proceedings, International Symposium on Low Power Design (Dana Point, California, April 23-26, 1995). ACM Press, New York, NY, 9-14.
    • (1995) Proceedings, International Symposium on Low Power Design , pp. 9-14
    • Raje, S.1    Sarrafzadeh, M.2
  • 15
    • 0029225181 scopus 로고
    • Power-profiler: Optimizing ASICs power consumption at the behavioral level
    • San Francisco, CA, June 12-16, 1995. ACM Press, New York, NY
    • SAN MARTIN, R. AND KNIGHT, J. P. 1995. Power-profiler: optimizing ASICs power consumption at the behavioral level. In Proceedings of the 32nd ACM/IEEE Design Automation Conference (San Francisco, CA, June 12-16, 1995). ACM Press, New York, NY, 42-47.
    • (1995) Proceedings of the 32nd ACM/IEEE Design Automation Conference , pp. 42-47
    • San Martin, R.1    Knight, J.P.2
  • 17
    • 0029193696 scopus 로고
    • Clustered voltage scaling technique for low-power design
    • Dana Point, California, April 23-26, 1995. ACM Press, New York, NY
    • USAMI, K. AND HOROWITZ, M. 1995. Clustered voltage scaling technique for low-power design. In Proceedings of the International Symposium on Low Power Design (Dana Point, California, April 23-26, 1995). ACM Press, New York, NY, 3-8.
    • (1995) Proceedings of the International Symposium on Low Power Design , pp. 3-8
    • Usami, K.1    Horowitz, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.