Dynamic clock management for low power applications in FPGAs

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 139-142

  Brynjolfson, Ian ^a   Zilic, Zeljko ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC VARIABLES CONTROL; FIELD PROGRAMMABLE GATE ARRAYS; NUMERICAL METHODS; PERFORMANCE;

COMBINATORIAL LOGIC ARCHITECTURE; DYNAMIC CLOCK MANAGEMENT; DYNAMIC PROGRAMMABLE CLOCK DIVIDERS; LOW POWER TECHNIQUES;

TIMING CIRCUITS;

EID: 0033682459     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)