VLSI array architecture with dynamic frequency clocking

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1996, Pages 137-140

  Ranganathan, N ^a   Vijaykrishnan, N ^a   Bhavanishankar, N ^a  

^a UNIVERSITY OF SOUTH FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; DIVIDING CIRCUITS (ARITHMETIC); FREQUENCY STABILITY; IMAGE PROCESSING; MULTIPLYING CIRCUITS; PIPELINE PROCESSING SYSTEMS; SIGNAL ENCODING; SWITCHING FUNCTIONS; TIMING CIRCUITS; VLSI CIRCUITS;

DYNAMIC FREQUENCY CLOCKING; LOGIC BLOCKS;

CELLULAR ARRAYS;

EID: 0030413616     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)