Telescopic Units: A new paradigm for performance optimization of VLSI designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 3, 1998, Pages 220-232

  Benini, Luca ^a,b   Macii, Enrico ^a,c   Poncino, Massimo ^a,c   De Micheli, Giovanni ^a,b  

^a IEEE   (United States)

^b STANFORD UNIVERSITY   (United States)

^c POLITECNICO DI TORINO   (Italy)

Author keywords

Circuit optimization; Design automation; Highspeed integrated circuits; Logic design; Synchronization

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; OPTIMIZATION; SYNCHRONIZATION; VLSI CIRCUITS;

TELESCOPIC UNITS; VARIABLE LATENCY UNITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032024306     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.700720     Document Type: Article

References (19)

1. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach. San Francisco, CA: Morgan Kaufmann, 1996.
2. S. F. Oberman and M. J. Flynn, "Design issues in division and other floating-point operations," IEEE Trans. Comput., vol. 46, pp. 154-161, Feb. 1997.
3. M. A. Kishinevsky, Concurrent Hardware: The Theory and Practice of Self-Timed Design. New York: Wiley, 1994.
4. R. I. Bahar, H. Cho, G. D. Hachtel, E. Macii, and F. Somenzi, "Timing analysis of combinational circuits using ADD's," presented at the EDTC-94: IEEE Ear. Design Test Conf. . pp. 625-629, Paris, France, Feb. 1994.
5. S. Hassoun and C. Ebeling, "Architectural retiming: Pipelining latencyconstrained circuits," presented at the DAC-33: ACM/IEEE Design Automation Conf., pp. 708-713, Las Vegas, NV, June 1996.
6. S. Nowick, "Design of a low-latency asynchronous adder using speculative completion," IEE P roc. Comput. Digital Techniques, vol. 143, pp. 301-307, Sept. 1996.
7. R. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Trans. Comput., vol. C-35, pp. 79-85, Aug. 1986.
8. R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, "Algebraic decision diagrams and their applications," Formal Methods Syst. Design, vol. 10, pp. 171-206, 1997.
9. L. Burgun, N. Dictus, A. Greiner, E. Prado Lopes, and C. Sarwary, "Multilevel optimization of very high complexity circuits," presented at the EuroDAC-94: IEEE Eur. Design Automation Conf., pp. 14-19, Grenoble, France, Sept. 1994.
10. F. Somenzi, "CUDD: University of Colorado decision diagram package, release 2.1.2," Dept. ECE, Univ. Colorado, Boulder, Tech. Rep., Apr. 1997.
11. K. Ravi and F. Somenzi, "High-density reachability analysis," presented at the ICCAD-95: IEEE/ACM Int. Conf. Computer-Aided Design, pp. 154-158, San Jose, CA, Nov. 1995.
12. L. Benini, E. Macii, and M. Poncino, "Telescopic units: Increasing the average throughput of pipelined designs by adaptive latency control," presented at the DAC-34: ACM/IEEE Design Automation Conf., pp. 22-27, Anaheim, CA, June 1997.
13. T. Shiple, "Formal analysis of synchronous circuits," Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley, 1996.
14. L. Benini, E. Macii, and M. Poncino, "Efficient controller design for telescopic units," presented at the ISIS-97: IEEE Int. Conf. Innovative Syst. in Silicon, pp. 290-299, Austin, TX, Oct. 1997.
15. G. De Micheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.
16. D. Ku and G. De Micheli, High-level Synthesis ofASIC's Under Timing and Synchronization Constraints. Norwell, MA: Kluwer, 1992.
17. L. Lavagno and A. Sangiovanni-Vincentelli, Algorithms for Synthesis and Testing of Asynchronous Circuits. Norwell, MA: Kluwer, 1993.
18. E. M. Sentovich, K. J. Singh, C. W. Moon, H. Savoij, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Sequential circuits design using synthesis and optimization," presented at the ICCD-92: IEEE Int. Conf. Comput. Design, pp. 328-333, Cambridge, MA, Oct. 1992.
19. S. Yang, "Logic synthesis and optimization benchmarks user guide version 3.0," MCNC: Microelectronics Center of North Carolina, Research Triangle Park, NC, Tech. Rep., Jan. 1991.