Instruction scheduling for low power on dynamically variable voltage processors

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2000, Pages 613-618

  Mansour, Mohammad M ^a   Mansour, Makram M ^a   Hajj, Ibrahim ^a   Shanbhag, Naresh ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Instruction scheduling; List scheduling; Variable voltage processors

Indexed keywords

BEHAVIORAL LEVEL; FUNCTIONAL UNITS; INSTRUCTION SCHEDULING; INSTRUCTION SCHEDULING ALGORITHM; LATTICE FILTERS; LIST-SCHEDULING; LOW POWER; LOW-POWER DESIGN; RESOURCE-CONSTRAINED; SCHEDULING OPERATIONS; VARIABLE VOLTAGE; VARIABLE-VOLTAGE PROCESSOR; VLSI DESIGN;

DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; VLSI CIRCUITS;

SCHEDULING ALGORITHMS;

EID: 3042568144     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2000.911614     Document Type: Conference Paper

References (5)

1. Yann-Rue Lin, Allen C.-H. Wu, "Scheduling Techniques for Variable Voltage Low Power Designs", ACM transactions on Design Automation of Electronic Systems, Vol.2, April 1997, pp. 81-97.
2. A. Chandrakasan, A. Potknojak, M. Rabaey, and R.W. Brodersen, "A system for power minimization using architectural transformation", Proceedings of the ICCAD, Nov. 1992, pp.300-303.
3. .Salil Raje, M. Sarrafzadeh, "Scheduling with Multiple Voltages", International symposium on Low Power Design, 1995, pp.9-14.
4. Steven S. Muchnick, "Advanced Compilw Design Implementation", Morgan Kauffman publishers, 1997.
5. John Proakis, Dimitris Manolakis, "Digital Signal Processing", Prentice Hall, third edition, 1996.