Low-power scheduling with resources operating at multiple voltages

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 6, 2000, Pages 536-543

  Shiue, Wen Tsong ^a   Chakrabarti, Chaitali ^a  

^a Arizona State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT;

LATENCY CONSTRAINED SCHEDULING; LOW POWER SCHEDULING; MULTIPLE VOLTAGE SCHEDULING; POWER CONSUMPTION; RESOURCE CONSTRAINED SCHEDULING;

VLSI CIRCUITS;

EID: 0033684369     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.847069     Document Type: Article

References (13)

1. [ l ] A. Chandrakasan and R. Brodersen, "Minimizing power consumption in digital CMOS circuits," in Proc. IEEE, vol. 83, Apr. 1995, pp. 498-523.
2. A. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and Brodersen, "Optimizing power using transformations," IEEE Trans. Computer-Aided Design, vol. 14, pp. 12-31, Jan. 1995.
3. A. Dasgupta and R. Karri, "Simultaneous scheduling and binding for low power minimization during microarchitecture synthesis," in Proc. Int. Symp. Low-Power Design, Apr. 1995, pp. 69-74.
4. A. Raghunathan and N. K. Jha, "Behavioral synthesis for low power," in Proc. IEEE Design Automation Conf., 1995.
5. E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," in Proc. Int. Symp. Low Power Design, 1995, pp. 99-104.
6. J.-M. Chang and M. Pedram, "Energy minimization using multiple supply voltages," IEEE Trans. VLSI Syst., vol. 5, Dec. 1997.
7. M. Takahashi, M. Hamada, T. Nishikawa, H. Arakida, T. Fujita, F. Hatori, S. Mita, K. Suzuki, A. Chiba, T. Terazawa, F. Sano, Y. Watanabe, K. Usami, M. Igarashi, T. Ishikawa, M. Kanazawa, T. Kuroda, and T. Furuyama, "A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme," IEEE]. Solid-State Circuits, vol. 33, pp. 1772-1780, Nov. 1998.
8. M. C. Johnson and K. Roy, "Datapath scheduling with multiple supply voltages and level converters," ACM Trans. Design Automat. Electron. Syst., vol. 2, no. 3, pp. 227-248, July 1997.
9. S. Raje and M. Sarrafzadeh, "Scheduling with two voltages under resource constraints," Dept. Elect. Eng. Comput. Sei., Northwestern Univ., Evanston, IL, Tech. Rep., 1995.
10. "Scheduling with multiple voltages," Integration: The VLSI J., vol. 23, pp. 37-59, 1997.
11. W.-T. Shiue and C. Chakrabarti, "Low power scheduling with resources operating at multiple voltages," in IEEE Int. Symp. Circuits and Systems, vol. 2, June 1998, pp. 43740.
12. Y.-R. Lin, C.-T. Hwang, and A. C.-H. Wu, "Scheduling techniques for variable voltage low power designs," ACM Trans. Design Automat. Electron. Syst., vol. 2, no. 2, pp. 81-97, April 1997.
13. R. Mehra and J. Rabaey, "Exploiting regularity for low-power design," in Proc. Int. Conf. Computer-Aided Design, 1996, pp. 166-172.